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32 - bit arm ? cortex ? - m3 fm3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04683 rev.*c revised july 11, 2017 mb9b 1 10t series the mb9b110t series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with high - performance and competitive cost. th ese s eries are based on the arm cortex - m3 processor with on - chip flash memory and sram, and have peripheral functions such as motor control timers, adcs and communication interfaces (uart, c sio, i 2 c, lin). the products which are described in this data sheet are placed into type 2 product categories in " fm3 family peripheral manual ". features 32 - bit arm cortex - m3 core ? processor version: r2p1 ? up to 144 mhz frequency operation ? memory protection unit (mpu): improves the reliability of an embedded system ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memory] ? up to 1 mbyte ? built - in flash memory accelerator system with 16 kbyte trace buffer memory the read access to flash memory can be achieved without wait cycle up to the operation frequency of 72mhz. even at the operation frequency more than 72 mhz, an equivalent access to flash memory can be obtained by flash memory accelerator system. ? security function for code protection [sram] this series on - chip sram is composed of two independent srams (sram0, sram1) . sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 64 kbytes. ? sram1: up to 64 kbytes. external bus interface ? supports sram, nor and nand flash memory devices ? up to 8 chips selected ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size : up to 256 mbytes ? supports address/data multiplex ? supports external rdy function multi - function serial interface (max 8 channels) ? 4 channels with 16steps9 - bit fifo (ch.4 to ch.7), 4 channels without fifo (ch.0 to ch.3) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically controls the transmission/reception with cts/rts (only for ch.4) ? various error d etection functions available (parity errors, framing errors, and overrun errors) [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function available [lin] ? lin protocol rev.2.1 supported ? full - duplex double buff er ? master/slave mode supported ? lin break field generation (can be changed to 13 - bit length to 16 - bit) ? lin break delimiter generation (can be changed to 1 - bit length to 4 - bit) ? various error detection functions available (parity errors, framing errors, and o verrun errors) [i 2 c] standard - mode (max 100 kbps) / fast - mode (max 400 kbps) supported
document number: 002 - 04683 rev.*c page 2 of 132 mb9b110t series dma controller (8 channels) the dma controller has a dedicated bus independent from the cpu, so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 bits (4 gbytes) ? transfer mode: block transfer/burst transfer/demand transfer ? transfer data type: byte/half - word/word ? tra nsfer block count: 1 to 16 ? number of transfers: 1 to 65536 a/d converter (max 32 channels) [12 - bit a/d converter] ? successive approximation type ? built - in 3units ? conversion time: 1.0 s @ 5 v ? priority conversion available (priority at 2 levels) ? scanning con version mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4 steps) base timer (max 16 channels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /3 2 - bit reload timer ? 16 - /32 - bit pwc timer general - purpose i/o port this series can use its pins as i/o ports when they are not used for an external bus or peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up control per pin ? capable of reading pin level directly ? built - in port relocate function ? up to 154 fast i/o ports@ 176 pin package ? some ports are 5 v tolerant i/o. see " pin assignment " to confirm the corresponding pins. multi - function timer (max 3 units) the multi - function timer is composed of the following block s. ? 16 - bit free - run timer 3 ch./unit ? input capture 4 ch./unit ? output compare 6 ch./unit ? a/d activati on compare 3 ch./unit ? waveform generator 3 ch./unit ? 16 - bit ppg timer 3 ch./unit the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function quadrature position/revolution counter (qprc) (max 3 channels) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use the counter as the up/down counter. ? the detection edge of three external event input pins ain, bin and zin is configurabl e. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters.operation mode is selectable from the followings for each channel. ? f ree - running ? periodic (=reload) ? one - shot watch counter the watch counter is used for wake up from low - power consumption mode. interval timer: up to 64 s(max)@ sub clock: 32.768 khz external interrupt controller unit ? up to 32 external interrupt input pins ? on e non - maskable interrupt (nmi) pin
document number: 002 - 04683 rev.*c page 3 of 132 mb9b110t series watchdog timer (2 channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a "hardware" watchdog and a "software" watchdog. the "ha rdware" watchdog timer is operated by the built - in low - speed cr oscillator. therefore, the "hardware" watchdog is active in any low - power consumption mode except stop mode . crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 clock and reset [clocks] selectable from five clock sources (2 external oscillators, 2 built - in cr oscillators, and main pll). ? main clock: 4 mhz to 48 mhz ? sub clock: 32.768 khz ? built - in high - speed cr clock: 4 mhz ? built - in low - speed c r clock: 100 khz ? main pll clock [resets] ? reset requests from initx pin ? power - on reset ? software reset ? watchdog timers reset ? low - voltage detection reset ? clock supervisor reset clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? when external clock failure (clock stop) is detected, reset is asserted. ? when external frequency anomaly is detected, interrupt or reset is asserted. low - voltage detector (lvd) this series includes 2 - stage moni toring of voltage on the vcc pins. when the voltage falls below the voltage set, low voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - power consumption mode three low - power consumption mod es supported. ? sleep ? timer ? stop debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm). power supply wide range voltage vcc = 2.7 v to 5.5 v
document number: 002 - 04683 re v.*c page 4 of 132 mb9b110t series contents features ................................ ................................ ................................ ................................ ................................ .......... 1 1. product lineup ................................ ................................ ................................ ................................ ...................... 6 2. packages ................................ ................................ ................................ ................................ ................................ 7 3. pin assignment ................................ ................................ ................................ ................................ ..................... 8 4. list of pin functions ................................ ................................ ................................ ................................ ........... 11 5. i/o circuit type ................................ ................................ ................................ ................................ .................... 58 6. handling precautions ................................ ................................ ................................ ................................ ......... 65 6.1 precautions for product design ................................ ................................ ................................ .......................... 65 6.2 precautions for package mounting ................................ ................................ ................................ ..................... 67 6.3 precautions for use environment ................................ ................................ ................................ ....................... 68 7. handling devices ................................ ................................ ................................ ................................ ................ 69 8. block diagram ................................ ................................ ................................ ................................ ..................... 72 9. memory si ze ................................ ................................ ................................ ................................ ........................ 73 10. memory map ................................ ................................ ................................ ................................ ........................ 73 11. pin status in each cpu state ................................ ................................ ................................ ............................. 76 12. electrical characteristics ................................ ................................ ................................ ................................ ... 80 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ 80 12.2 recommended operating conditions ................................ ................................ ................................ ................. 82 12.3 dc characteristics ................................ ................................ ................................ ................................ .............. 83 12.3.1 current rating ................................ ................................ ................................ ................................ ..................... 83 12.3.2 p in characteristics ................................ ................................ ................................ ................................ .............. 85 12.4 ac characteristics ................................ ................................ ................................ ................................ .............. 87 12.4.1 main clock input characteristics ................................ ................................ ................................ ......................... 87 12.4.2 sub clock input characteristics ................................ ................................ ................................ .......................... 88 12.4.3 internal cr oscillation characteristics ................................ ................................ ................................ ................ 88 12.4.4 operating conditions of main and usb pll ................................ ................................ ................................ ....... 89 12.4.5 reset input characteristics ................................ ................................ ................................ ................................ . 90 12.4.6 power - on reset timing ................................ ................................ ................................ ................................ ....... 90 12.4.7 external bus timing ................................ ................................ ................................ ................................ ............ 91 12.4.8 base timer input timing ................................ ................................ ................................ ................................ ... 101 12.4.9 csio/uart timing ................................ ................................ ................................ ................................ ........... 102 12.4.10 external input timing ................................ ................................ ................................ ................................ ..... 110 12.4.11 quadrature position/revolution counter timing ................................ ................................ ............................. 111 12.4.12 i 2 c timing ................................ ................................ ................................ ................................ ...................... 113 12.4.13 etm timing ................................ ................................ ................................ ................................ ................... 114 12.4.14 jtag timing ................................ ................................ ................................ ................................ .................. 115 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ ......... 116 12.6 low - voltage detection characteristics ................................ ................................ ................................ ............. 119 12.6.1 low - voltage detection reset ................................ ................................ ................................ ............................ 119 12.6.2 interrupt of low - voltage detection ................................ ................................ ................................ .................... 119 12.7 flash memory write/erase characteristics ................................ ................................ ................................ ...... 120 12.7.1 write / erase time ................................ ................................ ................................ ................................ .............. 120 12.7.2 write cycles and data hold time ................................ ................................ ................................ ........................ 120 12.8 return time from low - power consumption mode ................................ ................................ ........................... 121 12.8.1 return factor: interrupt ................................ ................................ ................................ ................................ ..... 121
document number: 002 - 04683 re v.*c page 5 of 132 mb9b110t series 12.8.2 return factor: reset ................................ ................................ ................................ ................................ ......... 123 13. ordering information ................................ ................................ ................................ ................................ ........ 125 14. package dimensions ................................ ................................ ................................ ................................ ........ 126 15. major changes ................................ ................................ ................................ ................................ .................. 129 document history ................................ ................................ ................................ ................................ ...................... 131 sales, solutions, and legal information ................................ ................................ ................................ .................. 132
document number: 002 - 04683 re v.*c page 6 of 132 mb9b110t series 1. product lineup memory size product name mb9bf116s/t mb9bf117s/t mb9bf118s/t on - chip flash memory 512 kbytes 768 kbytes 1 mbytes on - chip sram 64 kbytes 96 kbytes 128 kbytes function product name mb9bf116s mb9bf117s mb9bf118s mb9bf116t mb9bf117t mb9bf118t pin count 144 176/192 cpu cortex - m3 freq. 144 mhz supply voltage range 2.7 v to 5.5 v dmac 8 ch external bus interface addr:19 - bit (max) r/wdata:8 - /16 - bit (max) cs: 8 (max) support: sram, nor & nand flash memory addr:25 - bit (max) r/wdata:8 - /16 - bit (max) cs:8 (max) support: sram, nor & nand flash memory multi - function serial interface (uart/csio/lin/i 2 c) 8 ch. (max) ch.4 to ch.7: fifo (16steps 9 bits) ch.0 to ch.3: no fifo base timer (pwc/ reload timer/pwm/ppg) 16 ch. (max) mf - timer a/d activation compare 3 ch. 3 units (max) input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform g enerator 3 ch. ppg 3 ch. qprc 3 ch. (max) dual timer 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 32 pins (max) + nmi pin 1 i/o ports 122 pins (max) 154 pins (max) 12 - bit a/d converter 24 ch. (3 units) 32 ch. (3 units) csv (clock super visor ) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp/etm note: ? all si gnals of the peripheral function in each product cannot be allocated due to the pin count restriction of a package. it is necessary to use the port relocate function of the i/o port according to functions use. see " electrical characteristics 12.4 ac characteristics 12.4.3 internal cr oscillation characteristics " for accura cy of built - in cr .
document number: 002 - 04683 re v.*c page 7 of 132 mb9b110t series 2. packages product name package mb9bf116s mb9bf117s mb9bf118s mb9bf116t mb9bf117t mb9bf118t lqfp: lqs144 (0.5 mm pitch) ? - lqfp: lqp176 (0.5 mm pitch) - ? bga: lbe192 (0.8 mm pitch) - ? ? : supported note : ? see " package dimensions " for detailed information on each package.
document number: 002 - 04683 re v.*c page 8 of 132 mb9b110t series 3. pin assignment lqp176 (top view) n ote : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin.tioa09_0, tioa09_1, and tioa09_2 cannot be used as the external startup trigger input (tg in signal) at i/o mode 1 (timer full mode) of the base timer. see " 0 base timer " in " handling devices " for details. vss p81 p80 vcc pf5/sck6_2/int08_0/zin2_1 pf4/tiob06_0/sot6_2/int07_0/bin2_1 pf3/tioa06_0/sin6_2/int06_0/ain2_1 p60/sin5_0/tioa02_2/int15_1 p61/sot5_0/tiob02_2 p62/sck5_0/adtg_3 pd3/tiob03_2 pd2/sin4_0/tioa03_2/int00_2 pd1/sot4_0/tiob14_0/int31_1 pd0/sck4_0/tiob10_2/int30_1 pcf/cts4_0/tiob08_2 pce/rts4_0/tiob06_1 pcd pcc pcb vss vcc pca pc9 pc8 pc7/crout_1 pc6/tioa14_0 pc5/tioa10_2 pc4/tioa08_2 pc3/tioa06_1 pc2 pc1 pc0 p95/tiob13_0/rto25_1/int27_0/mad24_0 p94/tiob12_0/rto24_1/sck5_1/int26_0/mad23_0 p93/tiob11_0/rto23_1/sot5_1/mad22_0 p92/tiob10_0/rto22_1/sin5_1/mad21_0 p91/tiob09_0/rto21_1/int31_0/mad20_0 p90/tiob08_0/rto20_1/int30_0/mad19_0 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx vcc 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 vcc 1 132 vss pa0/rto20_0/tioa08_0/frck1_0 2 131 p83 pa1/rto21_0/tioa09_0/ic10_0 3 130 p82 pa2/rto22_0/tioa10_0/ic11_0 4 129 vcc pa3/rto23_0/tioa11_0/ic12_0 5 128 pf6/frck2_0/nmix pa4/rto24_0/tioa12_0/ic13_0/int03_0 6 127 p20/int05_0/crout_0/ain1_1/mad18_0 pa5/rto25_0/tioa13_0/int10_2 7 126 p21/sin0_0/int06_1/bin1_1 p05/traced0/tioa05_2/sin4_2/int00_1 8 125 p22/an31/sot0_0/tiob07_1/zin1_1 p06/traced1/tiob05_2/sot4_2/int01_1 9 124 p23/an30/sck0_0/tioa07_1/rto00_1 p07/traced2/adtg_0/sck4_2 10 123 p24/an29/sin2_1/int01_2/rto01_1/mad17_0 p08/traced3/tioa00_2/cts4_2 11 122 p25/an28/sot2_1/rto02_1/mad16_0 p09/traceclk/tiob00_2/rts4_2/dtti2x_0 12 121 p26/an27/sck2_1/rto03_1/mad15_0 p50/int00_0/ain0_2/sin3_1/rto10_0/ic20_0/moex_0 13 120 p27/an26/int02_2/rto04_1/mad14_0 p51/int01_0/bin0_2/sot3_1/rto11_0/ic21_0/mwex_0 14 119 p28/an25/adtg_4/int09_0/rto05_1/mad13_0 p52/int02_0/zin0_2/sck3_1/rto12_0/ic22_0/mdqm0_0 15 118 p29/an24/mad12_0 p53/sin6_0/tioa01_2/int07_2/rto13_0/ic23_0/mdqm1_0 16 117 pb7/an23/tiob12_1/int23_0/zin2_2 p54/sot6_0/tiob01_2/rto14_0/male_0 17 116 pb6/an22/tioa12_1/sck0_2/int22_0/bin2_2 p55/sck6_0/adtg_1/rto15_0/mrdy_0 18 115 pb5/an21/tiob11_1/sot0_2/int21_0/ain2_2 p56/sin1_0/int08_2/tioa09_2/dtti1x_0/mnale_0 19 114 pb4/an20/tioa11_1/sin0_2/int20_0 p57/sot1_0/tiob09_2/int16_1/mncle_0 20 113 pb3/an19/tiob10_1/int19_0 p58/sck1_0/tioa11_2/int17_1/mnwex_0 21 112 pb2/an18/tioa10_1/sck7_2/int18_0 p59/sin7_0/tiob11_2/int09_2/mnrex_0 22 111 pb1/an17/tiob09_1/sot7_2/int17_0 p5a/sot7_0/tioa13_1/int18_1/mcsx0_0 23 110 pb0/an16/tioa09_1/sin7_2/int16_0 p5b/sck7_0/tiob13_1/int19_1/mcsx1_0 24 109 vss p5c/tioa06_2/int28_0/ic20_1 25 108 avss p5d/tiob06_2/int29_0/dtti2x_1 26 107 avrh vss 27 106 avcc p30/ain0_0/tiob00_1/int03_2 28 105 p1f/an15/adtg_5/int29_1/tiob15_2/frck0_1/mad11_0 p31/bin0_0/tiob01_1/sck6_1/int04_2 29 104 p1e/an14/rts4_1/int28_1/tioa15_2/dtti0x_1/mad10_0 p32/zin0_0/tiob02_1/sot6_1/int05_2 30 103 p1d/an13/cts4_1/int27_1/tiob14_2/ic03_1/mad09_0 p33/int04_0/tiob03_1/sin6_1/adtg_6 31 102 p1c/an12/sck4_1/int26_1/tioa14_2/ic02_1/mad08_0 p34/frck0_0/tiob04_1 32 101 p1b/an11/sot4_1/int25_1/tiob13_2/ic01_1/mad07_0 p35/ic03_0/tiob05_1/int08_1 33 100 p1a/an10/sin4_1/int05_1/tioa13_2/ic00_1/mad06_0 p36/ic02_0/sin5_2/int09_1/tioa12_2/mcsx2_0 34 99 p19/an09/sck2_2/int22_1/mad05_0 p37/ic01_0/sot5_2/int10_1/tiob12_2/mcsx3_0 35 98 p18/an08/sot2_2/int21_1/mad04_0 p38/ic00_0/sck5_2/int11_1/mclkout_0 36 97 p17/an07/sin2_2/int04_1/mad03_0 p39/dtti0x_0/adtg_2 37 96 p16/an06/sck0_1/int20_1/mad02_0 p3a/rto00_0/tioa00_1 38 95 p15/an05/sot0_1/ic03_2/mad01_0 p3b/rto01_0/tioa01_1 39 94 p14/an04/sin0_1/int03_1/ic02_2/mad00_0 p3c/rto02_0/tioa02_1 40 93 p13/an03/sck1_1/ic01_2/mcsx4_0 p3d/rto03_0/tioa03_1 41 92 p12/an02/sot1_1/ic00_2/mcsx5_0 p3e/rto04_0/tioa04_1 42 91 p11/an01/sin1_1/int02_1/frck0_2/mcsx6_0 p3f/rto05_0/tioa05_1 43 90 p10/an00/mcsx7_0 vss 44 89 vcc 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 vcc p40/tioa00_0/rto10_1/int12_1 p41/tioa01_0/rto11_1/int13_1 p42/tioa02_0/rto12_1 p43/tioa03_0/rto13_1/adtg_7 p44/tioa04_0/rto14_1 p45/tioa05_0/rto15_1 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2 p49/tiob00_0/ic10_1/ain0_1/sot3_2 p4a/tiob01_0/ic11_1/bin0_1/sck3_2/madata00_0 p4b/tiob02_0/ic12_1/zin0_1/madata01_0 p4c/tiob03_0/ic13_1/sck7_1/ain1_2/madata02_0 p4d/tiob04_0/frck1_1/sot7_1/bin1_2/madata03_0 p4e/tiob05_0/int06_2/sin7_1/zin1_2/madata04_0 p70/tioa04_2/madata05_0 p71/int13_2/tiob04_2/madata06_0 p72/sin2_0/int14_2/ain2_0/madata07_0 p73/sot2_0/int15_2/bin2_0/madata08_0 p74/sck2_0/zin2_0/madata09_0 p75/sin3_0/adtg_8/int07_1/madata10_0 p76/sot3_0/tioa07_2/int11_2/madata11_0 p77/sck3_0/tiob07_2/int12_2/madata12_0 p78/ain1_0/tioa15_0/madata13_0 p79/bin1_0/tiob15_0/int23_1/madata14_0 p7a/zin1_0/int24_1/madata15_0 p7b/tiob07_0/int10_0 p7c/tioa07_0/int11_0 p7d/tioa14_1/frck2_1/int12_0 p7e/tiob14_1/ic21_1/int24_0 p7f/tioa15_1/ic22_1/int25_0 pf0/tiob15_1/sin1_2/int13_0/ic23_1 pf1/tioa08_1/sot1_2/int14_0 pf2/tiob08_1/sck1_2/int15_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 176
document number: 002 - 04683 re v.*c page 9 of 132 mb9b110t series lqs144 (top view) n ote : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. tioa09_0, tioa09_1, and tioa09 _2 cannot be used as the external startup trigger input (tgin signal) at i/o mode 1 (timer full mode) of the base timer. see " 0 base timer " in " handling devices " for details . vss p81 p80 vcc pf5/sck6_2/int08_0/zin2_1 p60/sin5_0/tioa02_2/int15_1 p61/sot5_0/tiob02_2 p62/sck5_0/adtg_3 pd3/tiob03_2 pd2/sin4_0/tioa03_2/int00_2 pd1/sot4_0/tiob14_0/int31_1 pd0/sck4_0/tiob10_2/int30_1 pcf/cts4_0/tiob08_2 pce/rts4_0/tiob06_1 pcd pcc pcb vss vcc pca pc9 pc8 pc7/crout_1 pc6/tioa14_0 pc5/tioa10_2 pc4/tioa08_2 pc3/tioa06_1 pc2 pc1 pc0 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx vcc 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vcc 1 108 vss pa0/rto20_0/tioa08_0/frck1_0 2 107 p83 pa1/rto21_0/tioa09_0/ic10_0 3 106 p82 pa2/rto22_0/tioa10_0/ic11_0 4 105 vcc pa3/rto23_0/tioa11_0/ic12_0 5 104 pf6/frck2_0/nmix pa4/rto24_0/tioa12_0/ic13_0/int03_0 6 103 p20/int05_0/crout_0/ain1_1/mad18_0 pa5/rto25_0/tioa13_0/int10_2 7 102 p21/sin0_0/int06_1/bin1_1 p05/traced0/tioa05_2/sin4_2/int00_1 8 101 p22/an31/sot0_0/tiob07_1/zin1_1 p06/traced1/tiob05_2/sot4_2/int01_1 9 100 p23/an30/sck0_0/tioa07_1/rto00_1 p07/traced2/adtg_0/sck4_2 10 99 p24/an29/sin2_1/int01_2/rto01_1/mad17_0 p08/traced3/tioa00_2/cts4_2 11 98 p25/an28/sot2_1/rto02_1/mad16_0 p09/traceclk/tiob00_2/rts4_2/dtti2x_0 12 97 p26/an27/sck2_1/rto03_1/mad15_0 p50/int00_0/ain0_2/sin3_1/rto10_0/ic20_0/moex_0 13 96 p27/an26/int02_2/rto04_1/mad14_0 p51/int01_0/bin0_2/sot3_1/rto11_0/ic21_0/mwex_0 14 95 p28/an25/adtg_4/int09_0/rto05_1/mad13_0 p52/int02_0/zin0_2/sck3_1/rto12_0/ic22_0/mdqm0_0 15 94 p29/an24/mad12_0 p53/sin6_0/tioa01_2/int07_2/rto13_0/ic23_0/mdqm1_0 16 93 vss p54/sot6_0/tiob01_2/rto14_0/male_0 17 92 avss p55/sck6_0/adtg_1/rto15_0/mrdy_0 18 91 avrh p56/sin1_0/int08_2/tioa09_2/dtti1x_0/mnale_0 19 90 avcc p57/sot1_0/tiob09_2/int16_1/mncle_0 20 89 p1f/an15/adtg_5/int29_1/tiob15_2/frck0_1/mad11_0 p58/sck1_0/tioa11_2/int17_1/mnwex_0 21 88 p1e/an14/rts4_1/int28_1/tioa15_2/dtti0x_1/mad10_0 p59/sin7_0/tiob11_2/int09_2/mnrex_0 22 87 p1d/an13/cts4_1/int27_1/tiob14_2/ic03_1/mad09_0 p5a/sot7_0/tioa13_1/int18_1/mcsx0_0 23 86 p1c/an12/sck4_1/int26_1/tioa14_2/ic02_1/mad08_0 p5b/sck7_0/tiob13_1/int19_1/mcsx1_0 24 85 p1b/an11/sot4_1/int25_1/tiob13_2/ic01_1/mad07_0 vss 25 84 p1a/an10/sin4_1/int05_1/tioa13_2/ic00_1/mad06_0 p36/ic02_0/sin5_2/int09_1/tioa12_2/mcsx2_0 26 83 p19/an09/sck2_2/int22_1/mad05_0 p37/ic01_0/sot5_2/int10_1/tiob12_2/mcsx3_0 27 82 p18/an08/sot2_2/int21_1/mad04_0 p38/ic00_0/sck5_2/int11_1/mclkout_0 28 81 p17/an07/sin2_2/int04_1/mad03_0 p39/dtti0x_0/adtg_2 29 80 p16/an06/sck0_1/int20_1/mad02_0 p3a/rto00_0/tioa00_1 30 79 p15/an05/sot0_1/ic03_2/mad01_0 p3b/rto01_0/tioa01_1 31 78 p14/an04/sin0_1/int03_1/ic02_2/mad00_0 p3c/rto02_0/tioa02_1 32 77 p13/an03/sck1_1/ic01_2/mcsx4_0 p3d/rto03_0/tioa03_1 33 76 p12/an02/sot1_1/ic00_2/mcsx5_0 p3e/rto04_0/tioa04_1 34 75 p11/an01/sin1_1/int02_1/frck0_2/mcsx6_0 p3f/rto05_0/tioa05_1 35 74 p10/an00/mcsx7_0 vss 36 73 vcc 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vcc p40/tioa00_0/rto10_1/int12_1 p41/tioa01_0/rto11_1/int13_1 p42/tioa02_0/rto12_1 p43/tioa03_0/rto13_1/adtg_7 p44/tioa04_0/rto14_1 p45/tioa05_0/rto15_1 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2 p49/tiob00_0/ic10_1/ain0_1/sot3_2 p4a/tiob01_0/ic11_1/bin0_1/sck3_2/madata00_0 p4b/tiob02_0/ic12_1/zin0_1/madata01_0 p4c/tiob03_0/ic13_1/sck7_1/ain1_2/madata02_0 p4d/tiob04_0/frck1_1/sot7_1/bin1_2/madata03_0 p4e/tiob05_0/int06_2/sin7_1/zin1_2/madata04_0 p70/tioa04_2/madata05_0 p71/int13_2/tiob04_2/madata06_0 p72/sin2_0/int14_2/ain2_0/madata07_0 p73/sot2_0/int15_2/bin2_0/madata08_0 p74/sck2_0/zin2_0/madata09_0 p75/sin3_0/adtg_8/int07_1/madata10_0 p76/sot3_0/tioa07_2/int11_2/madata11_0 p77/sck3_0/tiob07_2/int12_2/madata12_0 p78/ain1_0/tioa15_0/madata13_0 p79/bin1_0/tiob15_0/int23_1/madata14_0 p7a/zin1_0/int24_1/madata15_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 144
document number: 002 - 04683 re v.*c page 10 of 132 mb9b110t series lbe192 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. tioa09_0, tioa09_1, and tioa09_2 cannot be used as the external startup trigger input (tgin signal) at i/o mode 1 (timer full mode) of the base timer. see " 0 base timer " in " handling devices " for details. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a p81 p80 vcc vss pcd pcb vss vcc pc8 vss tck vcc b vss pa0 pf5 pf3 p61 pd1 pca pc1 p95 p92 tdo tms trstx vss c vcc pa1 pa2 pf4 p60 pd2 pcc pc5 pc0 p93 p90 tdi pf6 p83 d pa5 pa4 p05 p06 pa3 pd3 pce pc6 pc2 p94 p91 p21 p20 p82 e vss p07 p08 p09 p50 p62 pcf pc7 pc3 p25 p24 p23 p22 vcc f p51 p52 p53 p54 p55 p56 pd0 pc9 pc4 p29 p28 p27 p26 vss g vss p57 p58 p59 p5a p5b vss vss pb7 pb6 pb5 pb4 pb3 avss h p5c p5d p30 p31 p32 p33 vss vss p1f p1e pb2 pb1 pb0 avrh j vss p37 p36 p35 p34 p70 vss p76 p1d p1c p1b p1a p19 avcc k p38 p39 p3a p3b p4a p4e vss p74 p7b p7f p18 p16 p15 p17 l p3c p3d p3e p43 p49 p4d vss p73 p7a p7e p14 p13 p12 vss m vss p3f p42 p44 p48 p4c vss p72 p79 pf0 pf2 p11 p10 vcc n vcc p40 p41 p45 initx p4b vss p71 p78 p7d pf1 md0 md1 vss p c vss vcc x0a x1a vss p75 p77 p7c vss x0 x1
document number: 002 - 04683 re v.*c page 11 of 132 mb9b110t series 4. list of pin functions list of pin numbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 i ndicates the relocated port number. for these pins, the same function is provided on the same channel. use the extended port function register (epfr) to select the pin . pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 1 1 c1 vcc - 2 2 b2 pa0 g i rto20_0 tioa08_0 frck1_0 3 3 c2 pa1 g i rto21_0 tioa09_0 ic10_0 4 4 c3 pa2 g i rto22_0 tioa10_0 ic11_0 5 5 d5 pa3 g i rto23_0 tioa11_0 ic12_0 6 6 d2 pa4 g h rto24_0 tioa12_0 ic13_0 int03_0 7 7 d1 pa5 g h rto25_0 tioa13_0 int10_2 8 8 d3 p05 e f traced0 tioa05_2 sin4_2 int00_1
document number: 002 - 04683 re v.*c page 12 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 9 9 d4 p06 e f traced1 tiob05_2 sot4_2 int01_1 10 10 e2 p07 e g traced2 adtg_0 sck4_2 11 11 e3 p08 e g traced3 tioa00_2 cts4_2 12 12 e4 p09 e g traceclk tiob00_2 rts4_2 dtti2x_0 13 13 e5 p50 e h int00_0 ain0_2 sin3_1 rto10_0 ic20_0 moex_0 14 14 f1 p51 e h int01_0 bin0_2 sot3_1 rto11_0 ic21_0 mwex_0
document number: 002 - 04683 re v.*c page 13 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 15 15 f2 p52 e h int02_0 zin0_2 sck3_1 rto12_0 ic22_0 mdqm0_0 16 16 f3 p53 e h sin6_0 tioa01_2 int07_2 rto13_0 ic23_0 mdqm1_0 17 17 f4 p54 e i sot6_0 tiob01_2 rto14_0 male_0 18 18 f5 p55 e i sck6_0 adtg_1 rto15_0 mrdy_0 19 19 f6 p56 e h sin1_0 int08_2 tioa09_2 dtti1x_0 mnale_0 20 20 g2 p57 e h sot1_0 tiob09_2 int16_1 mncle_0
document number: 002 - 04683 re v.*c page 14 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 21 21 g3 p58 e h sck1_0 tioa11_2 int17_1 mnwex_0 22 22 g4 p59 e h sin7_0 tiob11_2 int09_2 mnrex_0 23 23 g5 p5a e h sot7_0 tioa13_1 int18_1 mcsx0_0 24 24 g6 p5b e h sck7_0 tiob13_1 int19_1 mcsx1_0 25 - h1 p5c e h tioa06_2 int28_0 ic20_1 26 - h2 p5d e h tiob06_2 int29_0 dtti2x_1 27 25 j1 vss - 28 - h3 p30 e h ain0_0 tiob00_1 int03_2
document number: 002 - 04683 re v.*c page 15 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 29 - h4 p31 e h bin0_0 tiob01_1 sck6_1 int04_2 30 - h5 p32 e h zin0_0 tiob02_1 sot6_1 int05_2 31 - h6 p33 e h int04_0 tiob03_1 sin6_1 adtg_6 32 - j5 p34 e i frck0_0 tiob04_1 33 - j4 p35 e h ic03_0 tiob05_1 int08_1 34 26 j3 p36 e h ic02_0 sin5_2 int09_1 tioa12_2 mcsx2_0 35 27 j2 p37 e h ic01_0 sot5_2 int10_1 tiob12_2 mcsx3_0
document number: 002 - 04683 re v.*c page 16 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 36 28 k1 p38 e h ic00_0 sck5_2 int11_1 mclkout_0 37 29 k2 p39 e i dtti0x_0 adtg_2 38 30 k3 p3a g i rto00_0 tioa00_1 39 31 k4 p3b g i rto01_0 tioa01_1 40 32 l1 p3c g i rto02_0 tioa02_1 41 33 l2 p3d g i rto03_0 tioa03_1 42 34 l3 p3e g i rto04_0 tioa04_1 43 35 m2 p3f g i rto05_0 tioa05_1 44 36 m1 vss - 45 37 n1 vcc - 46 38 n2 p40 g h tioa00_0 rto10_1 int12_1
document number: 002 - 04683 re v.*c page 17 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 47 39 n3 p41 g h tioa01_0 rto11_1 int13_1 48 40 m3 p42 g i tioa02_0 rto12_1 49 41 l4 p43 g i tioa03_0 rto13_1 adtg_7 50 42 m4 p44 g i tioa04_0 rto14_1 51 43 n4 p45 g i tioa05_0 rto15_1 52 44 p2 c - 53 45 p3 vss - 54 46 p4 vcc - 55 47 p5 p46 d m x0a 56 48 p6 p47 d n x1a 57 49 n5 initx b c 58 50 m5 p48 e h dtti1x_1 int14_1 sin3_2 59 51 l5 p49 e i tiob00_0 ic10_1 ain0_1 sot3_2
document number: 002 - 04683 re v.*c page 18 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 60 52 k5 p4a e i tiob01_0 ic11_1 bin0_1 sck3_2 madata00_0 61 53 n6 p4b e i tiob02_0 ic12_1 zin0_1 madata01_0 62 54 m6 p4c e i tiob03_0 ic13_1 sck7_1 ain1_2 madata02_0 63 55 l6 p4d e i tiob04_0 frck1_1 sot7_1 bin1_2 madata03_0 64 56 k6 p4e e h tiob05_0 int06_2 sin7_1 zin1_2 madata04_0 65 57 j6 p70 e i tioa04_2 madata05_0
document number: 002 - 04683 re v.*c page 19 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 66 58 n8 p71 e h int13_2 tiob04_2 madata06_0 67 59 m8 p72 e h sin2_0 int14_2 ain2_0 madata07_0 68 60 l8 p73 e h sot2_0 int15_2 bin2_0 madata08_0 69 61 k8 p74 e i sck2_0 zin2_0 madata09_0 70 62 p8 p75 e h sin3_0 adtg_8 int07_1 madata10_0 71 63 j8 p76 e h sot3_0 tioa07_2 int11_2 madata11_0 72 64 p9 p77 e h sck3_0 tiob07_2 int12_2 madata12_0
document number: 002 - 04683 re v.*c page 20 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 73 65 n9 p78 e i ain1_0 tioa15_0 madata13_0 74 66 m9 p79 e h bin1_0 tiob15_0 int23_1 madata14_0 - - e1 vss - - - g1 vss - 75 67 l9 p7a e h zin1_0 int24_1 madata15_0 76 - k9 p7b e h tiob07_0 int10_0 77 - p10 p7c e h tioa07_0 int11_0 78 - n10 p7d e h tioa14_1 frck2_1 int12_0 79 - l10 p7e e h tiob14_1 ic21_1 int24_0 80 - k10 p7f e h tioa15_1 ic22_1 int25_0
document number: 002 - 04683 re v.*c page 21 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 81 - m10 pf0 i * 1 h tiob15_1 sin1_2 int13_0 ic23_1 82 - n11 pf1 i * 1 h tioa08_1 sot1_2 int14_0 83 - m11 pf2 i * 1 h tiob08_1 sck1_2 int15_0 84 68 n13 pe0 c p md1 85 69 n12 md0 j d 86 70 p12 pe2 a a x0 87 71 p13 pe3 a b x1 88 72 n14 vss - 89 73 m14 vcc - - - l7 vss - - - k7 vss - 90 74 m13 p10 f k an00 mcsx7_0 91 75 m12 p11 f l an01 sin1_1 int02_1 frck0_2 mcsx6_0
document number: 002 - 04683 re v.*c page 22 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 92 76 l13 p12 f k an02 sot1_1 ic00_2 mcsx5_0 93 77 l12 p13 f k an03 sck1_1 ic01_2 mcsx4_0 94 78 l11 p14 f l an04 sin0_1 int03_1 ic02_2 mad00_0 95 79 k13 p15 f k an05 sot0_1 ic03_2 mad01_0 96 80 k12 p16 f l an06 sck0_1 int20_1 mad02_0 97 81 k14 p17 f l an07 sin2_2 int04_1 mad03_0 - - p7 vss - - - p11 vss - - - l14 vss -
document number: 002 - 04683 re v.*c page 23 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 98 82 k11 p18 f l an08 sot2_2 int21_1 mad04_0 99 83 j13 p19 f l an09 sck2_2 int22_1 mad05_0 100 84 j12 p1a f l an10 sin4_1 int05_1 tioa13_2 ic00_1 mad06_0 101 85 j11 p1b f l an11 sot4_1 int25_1 tiob13_2 ic01_1 mad07_0 102 86 j10 p1c f l an12 sck4_1 int26_1 tioa14_2 ic02_1 mad08_0
document number: 002 - 04683 re v.*c page 24 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 103 87 j9 p1d f l an13 cts4_1 int27_1 tiob14_2 ic03_1 mad09_0 104 88 h10 p1e f l an14 rts4_1 int28_1 tioa15_2 dtti0x_1 mad10_0 105 89 h9 p1f f l an15 adtg_5 int29_1 tiob15_2 frck0_1 mad11_0 106 90 j14 avcc - 107 91 h14 avrh - 108 92 g14 avss - 109 93 f14 vss - 110 - h13 pb0 f l an16 tioa09_1 sin7_2 int16_0 111 - h12 pb1 f l an17 tiob09_1 sot7_2 int17_0
document number: 002 - 04683 re v.*c page 25 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 112 - h11 pb2 f l an18 tioa10_1 sck7_2 int18_0 113 - g13 pb3 f l an19 tiob10_1 int19_0 114 - g12 pb4 f l an20 tioa11_1 sin0_2 int20_0 115 - g11 pb5 f l an21 tiob11_1 sot0_2 int21_0 ain2_2 - - g7 vss - - - j7 vss - 116 - g10 pb6 f l an22 tioa12_1 sck0_2 int22_0 bin2_2 117 - g9 pb7 f l an23 tiob12_1 int23_0 zin2_2 118 94 f10 p29 f k an24 mad12_0
document number: 002 - 04683 re v.*c page 26 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 119 95 f11 p28 f l an25 adtg_4 int09_0 rto05_1 mad13_0 120 96 f12 p27 f l an26 int02_2 rto04_1 mad14_0 121 97 f13 p26 f k an27 sck2_1 rto03_1 mad15_0 122 98 e10 p25 f k an28 sot2_1 rto02_1 mad16_0 123 99 e11 p24 f l an29 sin2_1 int01_2 rto01_1 mad17_0 124 100 e12 p23 f k an30 sck0_0 tioa07_1 rto00_1
document number: 002 - 04683 re v.*c page 27 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 125 101 e13 p22 f k an31 sot0_0 tiob07_1 zin1_1 126 102 d12 p21 e h sin0_0 int06_1 bin1_1 127 103 d13 p20 e h int05_0 crout_0 ain1_1 mad18_0 128 104 c13 pf6 i * 1 j frck2_0 nmix 129 105 e14 vcc - 130 106 d14 p82 h o 131 107 c14 p83 h o 132 108 b14 vss - 133 109 a13 vcc - 134 110 b13 p00 e e trstx 135 111 a12 p01 e e tck swclk 136 112 c12 p02 e e tdi 137 113 b12 p03 e e tms swdio 138 114 b11 p04 e e tdo swo
document number: 002 - 04683 re v.*c page 28 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 139 - c11 p90 e h tiob08_0 rto20_1 int30_0 mad19_0 - - a8 vss - 140 - d11 p91 e h tiob09_0 rto21_1 int31_0 mad20_0 141 - b10 p92 e i tiob10_0 rto22_1 sin5_1 mad21_0 142 - c10 p93 e i tiob11_0 rto23_1 sot5_1 mad22_0 143 - d10 p94 e h tiob12_0 rto24_1 sck5_1 int26_0 mad23_0 144 - b9 p95 e h tiob13_0 rto25_1 int27_0 mad24_0 145 115 c9 pc0 k q 146 116 b8 pc1 k q 147 117 d9 pc2 k q
document number: 002 - 04683 re v.*c page 29 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 148 118 e9 pc3 k q tioa06_1 149 119 f9 pc4 k q tioa08_2 150 120 c8 pc5 k q tioa10_2 - - a5 vss - 151 121 d8 pc6 k q tioa14_0 152 122 e8 pc7 l q crout_1 153 123 a10 pc8 k q 154 124 f8 pc9 k q 155 125 b7 pca k q 156 126 a9 vcc - 157 127 a11 vss - 158 128 a7 pcb l q 159 129 c7 pcc k q 160 130 a6 pcd k q 161 131 d7 pce l q rts4_0 tiob06_1 162 132 e7 pcf l q cts4_0 tiob08_2 163 133 f7 pd0 l r sck4_0 tiob10_2 int30_1 164 134 b6 pd1 l r sot4_0 tiob14_0 int31_1 - - n7 vss - - - g8 vss - - - h7 vss - - - h8 vss -
document number: 002 - 04683 re v.*c page 30 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 165 135 c6 pd2 l r sin4_0 tioa03_2 int00_2 166 136 d6 pd3 l q tiob03_2 167 137 e6 p62 e q sck5_0 adtg_3 168 138 b5 p61 e i sot5_0 tiob02_2 169 139 c5 p60 e h sin5_0 tioa02_2 int15_1 170 - b4 pf3 i * 1 h tioa06_0 sin6_2 int06_0 ain2_1 171 - c4 pf4 i * 1 h tiob06_0 sot6_2 int07_0 bin2_1 172 140 b3 pf5 i * 1 h sck6_2 int08_0 zin2_1
document number: 002 - 04683 re v.*c page 31 of 132 mb9b110t series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 173 141 a4 vcc - 174 142 a3 p80 h o 175 143 a2 p81 h o 176 144 b1 vss - - - m7 vss - * 1 : 5 v tolerant i/o
document number: 002 - 04683 re v.*c page 32 of 132 mb9b110t series list of pin functions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, the same function is provided on the same channel. use the extended port function register (epfr) to select the pin . module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 adc adtg_0 a/d converter external trigger input pin 10 10 e2 adtg_1 18 18 f5 adtg_2 37 29 k2 adtg_3 167 137 e6 adtg_4 119 95 f11 adtg_5 105 89 h9 adtg_6 31 - h6 adtg_7 49 41 l4 adtg_8 70 62 p8
document number: 002 - 04683 re v.*c page 33 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 adc an00 a/d converter analog input pin anxx describes adc ch.xx 90 74 m13 an01 91 75 m12 an02 92 76 l13 an03 93 77 l12 an04 94 78 l11 an05 95 79 k13 an06 96 80 k12 an07 97 81 k14 an08 98 82 k11 an09 99 83 j13 an10 100 84 j12 an11 101 85 j11 an12 102 86 j10 an13 103 87 j9 an14 104 88 h10 an15 105 89 h9 an16 110 - h13 an17 111 - h12 an18 112 - h11 an19 113 - g13 an20 114 - g12 an21 115 - g11 an22 116 - g10 an23 117 - g9 an24 118 94 f10 an25 119 95 f11 an26 120 96 f12 an27 121 97 f13 an28 122 98 e10 an29 123 99 e11 an30 124 100 e12 an31 125 101 e13
document number: 002 - 04683 re v.*c page 34 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 base timer 0 tioa0_0 base timer ch.0 tioa pin 46 38 n2 tioa0_1 38 30 k3 tioa0_2 11 11 e3 tiob0_0 base timer ch.0 tiob pin 59 51 l5 tiob0_1 28 - h3 tiob0_2 12 12 e4 base timer 1 tioa1_0 base timer ch.1 tioa pin 47 39 n3 tioa1_1 39 31 k4 tioa1_2 16 16 f3 tiob1_0 base timer ch.1 tiob pin 60 52 k5 tiob1_1 29 - h4 tiob1_2 17 17 f4 base timer 2 tioa2_0 base timer ch.2 tioa pin 48 40 m3 tioa2_1 40 32 l1 tioa2_2 169 139 c5 tiob2_0 base timer ch.2 tiob pin 61 53 n6 tiob2_1 30 - h5 tiob2_2 168 138 b5 base timer 3 tioa3_0 base timer ch.3 tioa pin 49 41 l4 tioa3_1 41 33 l2 tioa3_2 165 135 c6 tiob3_0 base timer ch.3 tiob pin 62 54 m6 tiob3_1 31 - h6 tiob3_2 166 136 d6 base timer 4 tioa4_0 base timer ch.4 tioa pin 50 42 m4 tioa4_1 42 34 l3 tioa4_2 65 57 j6 tiob4_0 base timer ch.4 tiob pin 63 55 l6 tiob4_1 32 - j5 tiob4_2 66 58 n8
document number: 002 - 04683 re v.*c page 35 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 base timer 5 tioa5_0 base timer ch.5 tioa pin 51 43 n4 tioa5_1 43 35 m2 tioa5_2 8 8 d3 tiob5_0 base timer ch.5 tiob pin 64 56 k6 tiob5_1 33 - j4 tiob5_2 9 9 d4 base timer 6 tioa6_0 base timer ch.6 tioa pin 170 - b4 tioa6_1 148 118 e9 tioa6_2 25 - h1 tiob6_0 base timer ch.6 tiob pin 171 - c4 tiob6_1 161 131 d7 tiob6_2 26 - h2 base timer 7 tioa07_0 base timer ch.7 tioa pin 77 - p10 tioa07_1 124 100 e12 tioa07_2 71 63 j8 tiob07_0 base timer ch.7 tiob pin 76 - k9 tiob07_1 125 101 e13 tiob07_2 72 64 p9 base timer 8 tioa08_0 base timer ch.8 tioa pin 2 2 b2 tioa08_1 82 - n11 tioa08_2 149 119 f9 tiob08_0 base timer ch.8 tiob pin 139 - c11 tiob08_1 83 - m11 tiob08_2 162 132 e7 base timer 9 tioa09_0 base timer ch.9 tioa pin 3 3 c2 tioa09_1 110 - h13 tioa09_2 19 19 f6 tiob09_0 base timer ch.9 tiob pin 140 - d11 tiob09_1 111 - h12 tiob09_2 20 20 g2
document number: 002 - 04683 re v.*c page 36 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 base timer 10 tioa10_0 base timer ch.10 tioa pin 4 4 c3 tioa10_1 112 - h11 tioa10_2 150 120 c8 tiob10_0 base timer ch.10 tiob pin 141 - b10 tiob10_1 113 - g13 tiob10_2 163 133 f7 base timer 11 tioa11_0 base timer ch.11 tioa pin 5 5 d5 tioa11_1 114 - g12 tioa11_2 21 21 g3 tiob11_0 base timer ch.11 tiob pin 142 - c10 tiob11_1 115 - g11 tiob11_2 22 22 g4 base timer 12 tioa12_0 base timer ch.12 tioa pin 6 6 d2 tioa12_1 116 - g10 tioa12_2 34 26 j3 tiob12_0 base timer ch.12 tiob pin 143 - d10 tiob12_1 117 - g9 tiob12_2 35 27 j2 base timer 13 tioa13_0 base timer ch.13 tioa pin 7 7 d1 tioa13_1 23 23 g5 tioa13_2 100 84 j12 tiob13_0 base timer ch.13 tiob pin 144 - b9 tiob13_1 24 24 g6 tiob13_2 101 85 j11 base timer 14 tioa14_0 base timer ch.14 tioa pin 151 121 d8 tioa14_1 78 - n10 tioa14_2 102 86 j10 tiob14_0 base timer ch.14 tiob pin 164 134 b6 tiob14_1 79 - l10 tiob14_2 103 87 j9
document number: 002 - 04683 re v.*c page 37 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 base timer 15 tioa15_0 base timer ch.15 tioa pin 73 65 n9 tioa15_1 80 - k10 tioa15_2 104 88 h10 tiob15_0 base timer ch.15 tiob pin 74 66 m9 tiob15_1 81 - m10 tiob15_2 105 89 h9 debugger swclk serial wire debug interface clock input 135 111 a12 swdio serial wire debug interface data input / output 137 113 b12 swo serial wire viewer output 138 114 b11 tck jtag test clock input 135 111 a12 tdi jtag test data input 136 112 c12 tdo jtag debug data output 138 114 b11 tms jtag test mode state input/output 137 113 b12 traceclk trace clk output of etm 12 12 e4 traced0 trace data output of etm 8 8 d3 traced1 9 9 d4 traced2 10 10 e2 traced3 11 11 e3 trstx jtag test reset i nput 134 110 b13
document number: 002 - 04683 re v.*c page 38 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external bus mad00_0 external bus interface address bus 94 78 l11 mad01_0 95 79 k13 mad02_0 96 80 k12 mad03_0 97 81 k14 mad04_0 98 82 k11 mad05_0 99 83 j13 mad06_0 100 84 j12 mad07_0 101 85 j11 mad08_0 102 86 j10 mad09_0 103 87 j9 mad10_0 104 88 h10 mad11_0 105 89 h9 mad12_0 118 94 f10 mad13_0 119 95 f11 mad14_0 120 96 f12 mad15_0 121 97 f13 mad16_0 122 98 e10 mad17_0 123 99 e11 mad18_0 127 103 d13 mad19_0 139 - c11 mad20_0 140 - d11 mad21_0 141 - b10 mad22_0 142 - c10 mad23_0 143 - d10 mad24_0 144 - b9 mcsx0_0 external bus interface chip select output pin 23 23 g5 mcsx1_0 24 24 g6 mcsx2_0 34 26 j3 mcsx3_0 35 27 j2 mcsx4_0 93 77 l12 mcsx5_0 92 76 l13 mcsx6_0 91 75 m12 mcsx7_0 90 74 m13
document number: 002 - 04683 re v.*c page 39 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external bus mdqm0_0 external bus interface byte mask signal output 15 15 f2 mdqm1_0 16 16 f3 moex_0 external bus interface read enable signal for sram 13 13 e5 mwex_0 external bus interface write enable signal for sram 14 14 f1 mnale_0 external bus interface ale signal to control nand flash memory output pin 19 19 f6 mncle_0 external bus interface cle signal to control nand flash memory output pin 20 20 g2 mnrex_0 external bus interface read enable signal to control nand flash memory 22 22 g4 mnwex_0 external bus interface write enable signal to control nand flash memory 21 21 g3 madata00_0 external bus interface data bus ( multiplexed bus to address output for multiplex ) 60 52 k5 madata01_0 61 53 n6 madata02_0 62 54 m6 madata03_0 63 55 l6 madata04_0 64 56 k6 madata05_0 65 57 j6 madata06_0 66 58 n8 madata07_0 67 59 m8 madata08_0 68 60 l8 madata09_0 69 61 k8 madata10_0 70 62 p8 madata11_0 71 63 j8 madata12_0 72 64 p9 madata13_0 73 65 n9 madata14_0 74 66 m9 madata15_0 75 67 l9 male_0 address latch enable signal for multiplex 17 17 f4 mrdy_0 external rdy input signal 18 18 f5 mclkout_0 external bus clock output 36 28 k1
document number: 002 - 04683 re v.*c page 40 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external interrupt int00_0 external interrupt request 00 input pin 13 13 e5 int00_1 8 8 d3 int00_2 165 135 c6 int01_0 external interrupt request 01 input pin 14 14 f1 int01_1 9 9 d4 int01_2 123 99 e11 int02_0 external interrupt request 02 input pin 15 15 f2 int02_1 91 75 m12 int02_2 120 96 f12 int03_0 external interrupt request 03 input pin 6 6 d2 int03_1 94 78 l11 int03_2 28 - h3 int04_0 external interrupt request 04 input pin 31 - h6 int04_1 97 81 k14 int04_2 29 - h4 int05_0 external interrupt request 05 input pin 127 103 d13 int05_1 100 84 j12 int05_2 30 - h5 int06_0 external interrupt request 06 input pin 170 - b4 int06_1 126 102 d12 int06_2 64 56 k6 int07_0 external interrupt request 07 input pin 171 - c4 int07_1 70 62 p8 int07_2 16 16 f3 int08_0 external interrupt request 08 input pin 172 140 b3 int08_1 33 - j4 int08_2 19 19 f6 int09_0 external interrupt request 09 input pin 119 95 f11 int09_1 34 26 j3 int09_2 22 22 g4 int10_0 external interrupt request 10 input pin 76 - k9 int10_1 35 27 j2 int10_2 7 7 d1
document number: 002 - 04683 re v.*c page 41 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external interrupt int11_0 external interrupt request 11 input pin 77 - p10 int11_1 36 28 k1 int11_2 71 63 j8 int12_0 external interrupt request 12 input pin 78 - n10 int12_1 46 38 n2 int12_2 72 64 p9 int13_0 external interrupt request 13 input pin 81 - m10 int13_1 47 39 n3 int13_2 66 58 n8 int14_0 external interrupt request 14 input pin 82 - n11 int14_1 58 50 m5 int14_2 67 59 m8 int15_0 external interrupt request 15 input pin 83 - m11 int15_1 169 139 c5 int15_2 68 60 l8 int16_0 external interrupt request 16 input pin 110 - h13 int16_1 20 20 g2 int17_0 external interrupt request 17 input pin 111 - h12 int17_1 21 21 g3 int18_0 external interrupt request 18 input pin 112 - h11 int18_1 23 23 g5 int19_0 external interrupt request 19 input pin 113 - g13 int19_1 24 24 g6 int20_0 external interrupt request 20 input pin 114 - g12 int20_1 96 80 k12 int21_0 external interrupt request 21 input pin 115 - g11 int21_1 98 82 k11 int22_0 external interrupt request 22 input pin 116 - g10 int22_1 99 83 j13 int23_0 external interrupt request 23 input pin 117 - g9 int23_1 74 66 m9 int24_0 external interrupt request 24 input pin 79 - l10 int24_1 75 67 l9 int25_0 external interrupt request 25 input pin 80 - k10 int25_1 101 85 j11
document number: 002 - 04683 re v.*c page 42 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external interrupt int26_0 external interrupt request 26 input pin 143 - d10 int26_1 102 86 j10 int27_0 external interrupt request 27 input pin 144 - b9 int27_1 103 87 j9 int28_0 external interrupt request 28 input pin 25 - h1 int28_1 104 88 h10 int29_0 external interrupt request 29 input pin 26 - h2 int29_1 105 89 h9 int30_0 external interrupt request 30 input pin 139 - c11 int30_1 163 133 f7 int31_0 external interrupt request 31 input pin 140 - d11 int31_1 164 134 b6 nmix non - maskable interrupt input 128 104 c13 gpio p00 general - purpose i/o port 0 134 110 b13 p01 135 111 a12 p02 136 112 c12 p03 137 113 b12 p04 138 114 b11 p05 8 8 d3 p06 9 9 d4 p07 10 10 e2 p08 11 11 e3 p09 12 12 e4
document number: 002 - 04683 re v.*c page 43 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p10 general - purpose i/o port 1 90 74 m13 p11 91 75 m12 p12 92 76 l13 p13 93 77 l12 p14 94 78 l11 p15 95 79 k13 p16 96 80 k12 p17 97 81 k14 p18 98 82 k11 p19 99 83 j13 p1a 100 84 j12 p1b 101 85 j11 p1c 102 86 j10 p1d 103 87 j9 p1e 104 88 h10 p1f 105 89 h9 p20 general - purpose i/o port 2 127 103 d13 p21 126 102 d12 p22 125 101 e13 p23 124 100 e12 p24 123 99 e11 p25 122 98 e10 p26 121 97 f13 p27 120 96 f12 p28 119 95 f11 p29 118 94 f10
document number: 002 - 04683 re v.*c page 44 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p30 general - purpose i/o port 3 28 - h3 p31 29 - h4 p32 30 - h5 p33 31 - h6 p34 32 - j5 p35 33 - j4 p36 34 26 j3 p37 35 27 j2 p38 36 28 k1 p39 37 29 k2 p3a 38 30 k3 p3b 39 31 k4 p3c 40 32 l1 p3d 41 33 l2 p3e 42 34 l3 p3f 43 35 m2 p40 general - purpose i/o port 4 46 38 n2 p41 47 39 n3 p42 48 40 m3 p43 49 41 l4 p44 50 42 m4 p45 51 43 n4 p46 55 47 p5 p47 56 48 p6 p48 58 50 m5 p49 59 51 l5 p4a 60 52 k5 p4b 61 53 n6 p4c 62 54 m6 p4d 63 55 l6 p4e 64 56 k6
document number: 002 - 04683 re v.*c page 45 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p50 general - purpose i/o port 5 13 13 e5 p51 14 14 f1 p52 15 15 f2 p53 16 16 f3 p54 17 17 f4 p55 18 18 f5 p56 19 19 f6 p57 20 20 g2 p58 21 21 g3 p59 22 22 g4 p5a 23 23 g5 p5b 24 24 g6 p5c 25 - h1 p5d 26 - h2 p60 general - purpose i/o port 6 169 139 c5 p61 168 138 b5 p62 167 137 e6 p70 general - purpose i/o port 7 65 57 j6 p71 66 58 n8 p72 67 59 m8 p73 68 60 l8 p74 69 61 k8 p75 70 62 p8 p76 71 63 j8 p77 72 64 p9 p78 73 65 n9 p79 74 66 m9 p7a 75 67 l9 p7b 76 - k9 p7c 77 - p10 p7d 78 - n10 p7e 79 - l10 p7f 80 - k10
document number: 002 - 04683 re v.*c page 46 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p80 general - purpose i/o port 8 174 142 a3 p81 175 143 a2 p82 130 106 d14 p83 131 107 c14 p90 general - purpose i/o port 9 139 - c11 p91 140 - d11 p92 141 - b10 p93 142 - c10 p94 143 - d10 p95 144 - b9 pa0 general - purpose i/o port a 2 2 b2 pa1 3 3 c2 pa2 4 4 c3 pa3 5 5 d5 pa4 6 6 d2 pa5 7 7 d1 pb0 general - purpose i/o port b 110 - h13 pb1 111 - h12 pb2 112 - h11 pb3 113 - g13 pb4 114 - g12 pb5 115 - g11 pb6 116 - g10 pb7 117 - g9
document number: 002 - 04683 re v.*c page 47 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio pc0 general - purpose i/o port c 145 115 c9 pc1 146 116 b8 pc2 147 117 d9 pc3 148 118 e9 pc4 149 119 f9 pc5 150 120 c8 pc6 151 121 d8 pc7 152 122 e8 pc8 153 123 a10 pc9 154 124 f8 pca 155 125 b7 pcb 158 128 a7 pcc 159 129 c7 pcd 160 130 a6 pce 161 131 d7 pcf 162 132 e7 pd0 general - purpose i/o port d 163 133 f7 pd1 164 134 b6 pd2 165 135 c6 pd3 166 136 d6 pe0 general - purpose i/o port e 84 68 n13 pe2 86 70 p12 pe3 87 71 p13 pf0 general - purpose i/o port f * 1 81 - m10 pf1 82 - n11 pf2 83 - m11 pf3 170 - b4 pf4 171 - c4 pf5 172 140 b3 pf6 128 104 c13
document number: 002 - 04683 re v.*c page 48 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function serial 0 sin0_0 multi - function serial interface ch.0 input pin 126 102 d12 sin0_1 94 78 l11 sin0_2 114 - g12 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio (operation modes 0 to 2) and as sda0 when it is used in an i 2 c (operation mode 4). 125 101 e13 sot0_1 (sda0_1) 95 79 k13 sot0_2 (sda0_2) 115 - g11 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio (operation modes 0 to 2) and as scl0 when it is used in an i 2 c (operation mode 4). 124 100 e12 sck0_1 (scl0_1) 96 80 k12 sck0_2 (scl0_2) 116 - g10 multi - function serial 1 sin1_0 multi - function serial interface ch.1 input pin 19 19 f6 sin1_1 91 75 m12 sin1_2 81 - m10 sot1_0 (sda1_0) multi - function serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/csio (operation modes 0 to 2) and as sda1 when it is used in an i 2 c (operation mode 4). 20 20 g2 sot1_1 (sda1_1) 92 76 l13 sot1_2 (sda1_2) 82 - n11 sck1_0 (scl1_0) multi - function serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a uart/csio (operation modes 0 to 2) and as scl1 when it is used in an i 2 c (operation mode 4). 21 21 g3 sck1_1 (scl1_1) 93 77 l12 sck1_2 (scl1_2) 83 - m11
document number: 002 - 04683 re v.*c page 49 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function serial 2 sin2_0 multi - function serial interface ch.2 input pin 67 59 m8 sin2_1 123 99 e11 sin2_2 97 81 k14 sot2_0 (sda2_0) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio (operation modes 0 to 2) and as sda2 when it is used in an i 2 c (operation mode 4). 68 60 l8 sot2_1 (sda2_1) 122 98 e10 sot2_2 (sda2_2) 98 82 k11 sck2_0 (scl2_0) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a uart/csio (operation modes 0 to 2) and as scl2 when it is used in an i 2 c (operation mode 4). 69 61 k8 sck2_1 (scl2_1) 121 97 f13 sck2_2 (scl2_2) 99 83 j13 multi - function serial 3 sin3_0 multi - function serial interface ch.3 input pin 70 62 p8 sin3_1 13 13 e5 sin3_2 58 50 m5 sot3_0 (sda3_0) multi - function serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio (operation modes 0 to 2) and as sda3 when it is used in an i 2 c (operation mode 4). 71 63 j8 sot3_1 (sda3_1) 14 14 f1 sot3_2 (sda3_2) 59 51 l5 sck3_0 (scl3_0) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a uart/csio (operation modes 0 to 2) and as scl3 when it is used in an i 2 c (operation mode 4). 72 64 p9 sck3_1 (scl3_1) 15 15 f2 sck3_2 (scl3_2) 60 52 k5
document number: 002 - 04683 re v.*c page 50 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function serial 4 sin4_0 multi - function serial interface ch.4 input pin 165 135 c6 sin4_1 100 84 j12 sin4_2 8 8 d3 sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio (operation modes 0 to 2) and as sda4 when it is used in an i 2 c (operation mode 4). 164 134 b6 sot4_1 (sda4_1) 101 85 j11 sot4_2 (sda4_2) 9 9 d4 sck4_0 (scl4_0) multi - function serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a uart/csio (operation modes 0 to 2) and as scl4 when it is used in an i 2 c (operation mode 4). 163 133 f7 sck4_1 (scl4_1) 102 86 j10 sck4_2 (scl4_2) 10 10 e2 rts4_0 multi - function serial interface ch.4 rts output pin 161 131 d7 rts4_1 104 88 h10 rts4_2 12 12 e4 cts4_0 multi - function serial interface ch.4 cts input pin 162 132 e7 cts4_1 103 87 j9 cts4_2 11 11 e3 multi - function serial 5 sin5_0 multi - function serial interface ch.5 input pin 169 139 c5 sin5_1 141 - b10 sin5_2 34 26 j3 sot5_0 (sda5_0) multi - function serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio (operation modes 0 to 2) and as sda5 when it is used in an i 2 c (operation mode 4). 168 138 b5 sot5_1 (sda5_1) 142 - c10 sot5_2 (sda5_2) 35 27 j2 sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a uart/csio (operation modes 0 to 2) and as scl5 when it is used in an i 2 c (operation mode 4). 167 137 e6 sck5_1 (scl5_1) 143 - d10 sck5_2 (scl5_2) 36 28 k1
document number: 002 - 04683 re v.*c page 51 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function serial 6 sin6_0 multi - function serial interface ch.6 input pin 16 16 f3 sin6_1 31 - h6 sin6_2 170 - b4 sot6_0 (sda6_0) multi - function serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio (operation modes 0 to 2) and as sda6 when it is used in an i 2 c (operation mode 4). 17 17 f4 sot6_1 (sda6_1) 30 - h5 sot6_2 (sda6_2) 171 - c4 sck6_0 (scl6_0) multi - function serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a uart/csio (operation modes 0 to 2) and as scl6 when it is used in an i 2 c (operation mode 4). 18 18 f5 sck6_1 (scl6_1) 29 - h4 sck6_2 (scl6_2) 172 140 b3 multi - function serial 7 sin7_0 multi - function serial interface ch.7 input pin 22 22 g4 sin7_1 64 56 k6 sin7_2 110 - h13 sot7_0 (sda7_0) multi - function serial interface ch.7 output pin. this pin operates as sot7 when it is used in a uart/csio (operation modes 0 to 2) and as sda7 when it is used in an i 2 c (operation mode 4). 23 23 g5 sot7_1 (sda7_1) 63 55 l6 sot7_2 (sda7_2) 111 - h12 sck7_0 (scl7_0) multi - function serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a uart/csio (operation modes 0 to 2) and as scl7 when it is used in an i 2 c (operation mode 4). 24 24 g6 sck7_1 (scl7_1) 62 54 m6 sck7_2 (scl7_2) 112 - h11
document number: 002 - 04683 re v.*c page 52 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function timer 0 dtti0x_0 input signal of waveform generator to control outputs rto00 to rto05 of multi - function timer 0. 37 29 k2 dtti0x_1 104 88 h10 frck0_0 16 - bit free - run timer ch.0 external clock input pin 32 - j5 frck0_1 105 89 h9 frck0_2 91 75 m12 ic00_0 16 - bit input capture input pin of multi - function timer 0 icxx describes channel number. 36 28 k1 ic00_1 100 84 j12 ic00_2 92 76 l13 ic01_0 35 27 j2 ic01_1 101 85 j11 ic01_2 93 77 l12 ic02_0 34 26 j3 ic02_1 102 86 j10 ic02_2 94 78 l11 ic03_0 33 - j4 ic03_1 103 87 j9 ic03_2 95 79 k13 rto00_0 (ppg00_0) waveform generator output of multi - function timer 0 this pin operates as ppg00 when it is used in ppg0 output modes. 38 30 k3 rto00_1 (ppg00_1) 124 100 e12 rto01_0 (ppg00_0) waveform generator output of multi - function timer 0 this pin operates as ppg00 when it is used in ppg0 output modes. 39 31 k4 rto01_1 (ppg00_1) 123 99 e11 rto02_0 (ppg02_0) waveform generator output of multi - function timer 0 this pin operates as ppg02 when it is used in ppg0 output modes. 40 32 l1 rto02_1 (ppg02_1) 122 98 e10 rto03_0 (ppg02_0) waveform generator output of multi - function timer 0 this pin operates as ppg02 when it is used in ppg0 output modes. 41 33 l2 rto03_1 (ppg02_1) 121 97 f13 rto04_0 (ppg04_0) waveform generator output of multi - function timer 0 this pin operates as ppg04 when it is used in ppg0 output modes. 42 34 l3 rto04_1 (ppg04_1) 120 96 f12 rto05_0 (ppg04_0) waveform generator output of multi - function timer 0 this pin operates as ppg04 when it is used in ppg0 output modes. 43 35 m2 rto05_1 (ppg04_1) 119 95 f11
document number: 002 - 04683 re v.*c page 53 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function timer 1 dtti1x_0 input signal of waveform generator to control outputs rto10 to rto15 of multi - function timer 1. 19 19 f6 dtti1x_1 58 50 m5 frck1_0 16 - bit free - run timer ch.1 external clock input pin 2 2 b2 frck1_1 63 55 l6 ic10_0 16 - bit input capture input pin of multi - function timer 1. icxx describes channel number 3 3 c2 ic10_1 59 51 l5 ic11_0 4 4 c3 ic11_1 60 52 k5 ic12_0 5 5 d5 ic12_1 61 53 n6 ic13_0 6 6 d2 ic13_1 62 54 m6 rto10_0 (ppg10_0) waveform generator output of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 13 13 e5 rto10_1 (ppg10_1) 46 38 n2 rto11_0 (ppg10_0) waveform generator output of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 14 14 f1 rto11_1 (ppg10_1) 47 39 n3 rto12_0 (ppg12_0) waveform generator output of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 15 15 f2 rto12_1 (ppg12_1) 48 40 m3 rto13_0 (ppg12_0) waveform generator output of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 16 16 f3 rto13_1 (ppg12_1) 49 41 l4 rto14_0 (ppg14_0) waveform generator output of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 17 17 f4 rto14_1 (ppg14_1) 50 42 m4 rto15_0 (ppg14_0) waveform generator output of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 18 18 f5 rto15_1 (ppg14_1) 51 43 n4
document number: 002 - 04683 re v.*c page 54 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi - function timer 2 dtti2x_0 input signal of waveform generator to control outputs rto20 to rto25 of multi - function timer 2. 12 12 e4 dtti2x_1 26 - h2 frck2_0 16 - bit free - run timer ch.2 external clock input pin 128 104 c13 frck2_1 78 - n10 ic20_0 16 - bit input capture input pin of multi - function timer 2. icxx describes channel number. 13 13 e5 ic20_1 25 - h1 ic21_0 14 14 f1 ic21_1 79 - l10 ic22_0 15 15 f2 ic22_1 80 - k10 ic23_0 16 16 f3 ic23_1 81 - m10 rto20_0 (ppg20_0) waveform generator output of multi - function timer 2. this pin operates as ppg20 when it is used in ppg2 output modes. 2 2 b2 rto20_1 (ppg20_1) 139 - c11 rto21_0 (ppg20_0) wave f orm generator output of multi - function timer 2. this pin operates as ppg20 when it is used in ppg2 output modes. 3 3 c2 rto21_1 (ppg20_1) 140 - d11 rto22_0 (ppg22_0) waveform generator output of multi - function timer 2. this pin operates as ppg22 when it is used in ppg2 output modes. 4 4 c3 rto22_1 (ppg22_1) 141 - b10 rto23_0 (ppg22_0) waveform generator output of multi - function timer 2. this pin operates as ppg22 when it is used in ppg2 output modes. 5 5 d5 rto23_1 (ppg22_1) 142 - c10 rto24_0 (ppg24_0) waveform generator output of multi - function timer 2. this pin operates as ppg24 when it is used in ppg2 output modes. 6 6 d2 rto24_1 (ppg24_1) 143 - d10 rto25_0 (ppg24_0) waveform generator output of multi - function timer 2. this pin operates as ppg24 when it is used in ppg2 output modes. 7 7 d1 rto25_1 (ppg24_1) 144 - b9
document number: 002 - 04683 re v.*c page 55 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 28 - h3 ain0_1 59 51 l5 ain0_2 13 13 e5 bin0_0 qprc ch.0 bin input pin 29 - h4 bin0_1 60 52 k5 bin0_2 14 14 f1 zin0_0 qprc ch.0 zin input pin 30 - h5 zin0_1 61 53 n6 zin0_2 15 15 f2 quadrature position/ revolution counter 1 ain1_0 qprc ch.1 ain input pin 73 65 n9 ain1_1 127 103 d13 ain1_2 62 54 m6 bin1_0 qprc ch.1 bin input pin 74 66 m9 bin1_1 126 102 d12 bin1_2 63 55 l6 zin1_0 qprc ch.1 zin input pin 75 67 l9 zin1_1 125 101 e13 zin1_2 64 56 k6 quadrature position/ revolution counter 2 ain2_0 qprc ch.2 ain input pin 67 59 m8 ain2_1 170 - b4 ain2_2 115 - g11 bin2_0 qprc ch.2 bin input pin 68 60 l8 bin2_1 171 - c4 bin2_2 116 - g10 zin2_0 qprc ch.2 zin input pin 69 61 k8 zin2_1 172 140 b3 zin2_2 117 - g9 r eset initx external reset input. a reset is valid when initx="l". 57 49 n5 mode md0 mode 0 p in. during normal operation, md0="l" must be input. during serial programming to f lash memory, md0="h" must be input. 85 69 n12 md1 mode 1 p in. during serial programming to f lash memory, md1="l" must be input. 84 68 n13
document number: 002 - 04683 re v.*c page 56 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 p ower vcc power supply pin 1 1 c1 vcc power supply p in 45 37 n1 vcc power supply pin 54 46 p4 vcc power supply pin 89 73 m14 vcc power supply pin 133 109 a13 vcc power supply pin 173 141 a4 vcc power supply pin 129 105 e14 vcc power supply pin 156 126 a9 gnd vss gnd pin 27 25 j1 vss gnd pin 44 36 m1 vss gnd pin 53 45 p3 vss gnd pin 88 72 n14 vss gnd pin 109 93 f14 vss gnd pin 132 108 b14 vss gnd pin 157 127 a11 vss gnd pin 176 144 b1 vss gnd pin - - e1 vss gnd pin - - g1 vss gnd pin - - p7 vss gnd pin - - p11 vss gnd pin - - l14 vss gnd pin - - a8 vss gnd pin - - a5 vss gnd pin - - n7 vss gnd pin - - m7 vss gnd pin - - l7 vss gnd pin - - k7 vss gnd pin - - j7 vss gnd pin - - g7 vss gnd pin - - h7 vss gnd pin - - h8 vss gnd pin - - g8 c lock x0 main clock (oscillation) input pin 86 70 p12 x0a sub clock (oscillation) input pin 55 47 p5 x1 main clock (oscillation) i/o pin 87 71 p13 x1a sub clock (oscillation) i/o pin 56 48 p6 crout_0 built - in high - speed cr oscillation clock output port 127 103 d13 crout_1 152 122 e8 analog p ower avcc a/d converter analog power supply pin 106 90 j14 avrh a/d converter analog reference voltage input pin 107 91 h14
document number: 002 - 04683 re v.*c page 57 of 132 mb9b110t series module pin name function pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 analog gnd avss a/d converter gnd pin 108 92 g14 c pin c power supply stabilization capacity pin 52 44 p2 note : ? while this device contains a test access port (tap) based on the ieee 1149.1 - 2001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other devices with different functionality. the tap pins may also be configurable for purposes other than access to the tap controller.
document number: 002 - 04683 re v.*c page 58 of 132 mb9b110t series 5. i /o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor: approximately 1 m ? with standby mode control whe n the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control
document number: 002 - 04683 re v.*c page 59 of 132 mb9b110t series type circuit remarks b ? cmos level hysteresis input ? pull - up resistor: approximately 50 k c ? open drain output ? cmos level hysteresis input pull - up resistor digital input digital input control pin n-ch
document number: 002 - 04683 re v.*c page 60 of 132 mb9b110t series type circuit remarks d i t is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor: approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control
document number: 002 - 04683 re v.*c page 61 of 132 mb9b110t series type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b i nput is available digital output digital output pull - up resistor control digital input standby mode control digital output digital output pull - up resistor control digital input standby mode control analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 04683 re v.*c page 62 of 132 mb9b110t series type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 20.5 ma, i ol =18.5 ma digital output digital output pull - up resistor control digital input standby mode control digital output digital output digital input standby mode control p-ch p-ch n-ch r p-ch n-ch r
document number: 002 - 04683 re v.*c page 63 of 132 mb9b110t series type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5 v tolerant ? with standby mode control ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off j cmos level hysteresis input k ? cmos level output ? ttl level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 50 k ? i oh = - 4 ma, i ol = 4 ma digital output digital output pull - up resistor control digital input standby mode control digital output digital output digital input standby mode control mode input p-ch p-ch n-ch r p-ch n-ch r
document number: 002 - 04683 re v.*c page 64 of 132 mb9b110t series type circuit remarks l ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 50 k ? i oh = - 8 ma, i ol = 8 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available digital output digital output pull - up resistor control digital input standby mode control p-ch p-ch n-ch r
document number: 002 - 04683 re v.*c page 65 of 132 mb9b110t series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended opera ting conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applic ation outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outp ut functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device . try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditions if pr esent for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be conne c ted through an appropriate resistance to a power supply pin or ground pin.
document number: 002 - 04683 re v.*c page 66 of 132 mb9b110t series latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junct ions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reli ability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulations and standards most countries in the world have established standards and regulations regarding s afety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must prot ect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. precautions r elated to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). ca ution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (s uch a s aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arisi ng from such use without prior approval.
document number: 002 - 04683 re v.*c page 67 of 132 mb9b110t series 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress recommended cond itions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by u sing a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes le ads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contac ts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. surface mount type surface mount packaging has longer an d thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to op en connections caused by deformed pins, or short ing due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress rank ing of recommended conditions. lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reduc ing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h
document number: 002 - 04683 re v.*c page 68 of 132 mb9b110t series static electricity because semiconductor devices are particularly susc eptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of co nductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assem blies. 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in s uch conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shie lding as ap propriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 04683 re v.*c page 69 of 132 mb9b110t series 7. handling devices power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in ord er to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the ris e in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pins and gnd pins of this device at low impedance. it is a lso advisable that a ceramic capacitor of approximately 0 .1 f be connected as a bypass capacitor between each power supply pins and gnd pins , between avcc pin and avss pin near this device. stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 h z/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. crystal oscillator circuit noise near th e x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. using an external clock when using an external clock, the clock signal should be input to the x0 ,x0a pin only and the x1 and x1a pin s should be kept open. handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disabled. however, i 2 c pins need to keep the electrical c haracteristic like other pins and not to connect to the external i 2 c bus system with power off. example of using an external clock device x0(x0a) x1(x1a) open
document number: 002 - 04683 re v.*c page 70 of 132 mb9b110t series c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteri stics). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventin g the device erroneously switching to test mode due to noise. notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter, connect avcc =vcc and avss = vss. turning on: vcc avcc avrh turning off: avrh avcc vcc device c vss cs gnd
document number: 002 - 04683 re v.*c page 71 of 132 mb9b110t series serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication.therefore, design a printed circuit board so as to avoid noise.consider the case of receiving wrong data due to noi se, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. differences in features among the products with different memory sizes and between flash products and mask products the electric ch aracteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between f lash products and mask products are different because chip layout and memory struct ures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics . base timer in the case of using ch.8 and ch.9 at i/o mode 1 (timer full mode), the tioa09 pin cannot be used for external startup trigger input (tgin). be sure to use the pin with making esg1 and esg2 bits of the timer control register (ch.9 - tmcr) in the base timer to be "0b00" in order to disable trigger input.
document number: 002 - 04683 re v.*c page 72 of 132 mb9b110t series 8. block diagram note : ? the following items vary dep ending on the package. ? external bus interface pin numbers ? 12 - bit a/d converter channel numbers a h b - a p b b r i d g e : a p b 2 ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 0 ( m a x 7 2 m h z ) f l a s h i / f c o r t e x - m 3 c o r e 1 4 4 m h z ( m a x ) c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . o n - c h i p f l a s h 5 1 2 k b y t e / 7 6 8 k b y t e / 1 0 2 4 k b y t e m u l t i - f u n c t i o n t i m e r 3 m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 t o c h . 7 ) h w f l o w c o n t r o l ( c h . 4 ) 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 3 c h . 1 6 - b i t p p g 3 c h . w a t c h c o u n t e r u n i t 0 g p i o c s v l v d e x t e r n a l i n t e r r u p t c o n t r o l l e r 3 2 - p i n + n m i p o w e r o n r e s e t t p i u r o m t a b l e e t m s r a m 0 3 2 / 4 8 / 6 4 k b y t e s w j - d p s r a m 1 3 2 / 4 8 / 6 4 k b y t e i d s y s m b 9 b f 1 1 6 / 1 1 7 / 1 1 8 b a s e t i m e r 1 6 - b i t 1 6 c h . / 3 2 - b i t 8 c h . n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r u n i t 1 u n i t 2 t r s t x , t c k , t d i , t m s t r a c e d [ 3 : 0 ] , t r a c e c l k a v c c , a v s s , a v r h a n [ 3 1 : 0 0 ] t i o a [ 1 5 : 0 0 ] t i o b [ 1 5 : 0 0 ] i c 0 [ 3 : 0 ] d t t i [ 2 : 0 ] x r t o 0 [ 5 : 0 ] f r c k [ 2 : 0 ] c t d o s c k [ 7 : 0 ] s i n [ 7 : 0 ] s o t [ 7 : 0 ] i n t [ 3 1 : 0 0 ] n m i x i n i t x m o d e - c t r l i r q - m o n i t o r p i n - f u n c t i o n - c t r l m d [ 1 : 0 ] r e g u l a t o r q p r c 3 c h . a i n [ 2 : 0 ] b i n [ 2 : 0 ] z i n [ 2 : 0 ] l v d c t r l c r c a c c e l e r a t o r i c 1 [ 3 : 0 ] a d t g [ 8 : 0 ] r t s 4 c t s 4 e x t e r n a l b u s i / f m a d [ 2 4 : 0 0 ] m a d a t a [ 1 5 : 0 0 ] m c s x [ 7 : 0 ] , m o e x , m w e x , m n a l e , m n c l e , m n w e x , m n r e x , m d q m [ 1 : 0 ] m a l e m r d y m c l k o u t r t o 1 [ 5 : 0 ] m p u t r a c e b u f f e r ( 1 6 k b y t e ) i c 2 [ 3 : 0 ] r t o 2 [ 5 : 0 ] p 0 x , p 1 x , . . . p f x x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z x 1 a m u l t i - l a y e r a h b ( m a x 1 4 4 m h z ) a h b - a h b b r i d g e ( s l a v e )
document number: 002 - 04683 re v.*c page 73 of 132 mb9b110t series 9. memory size see " memory size " in " product lineup " to confirm the memory size. 10. memory map memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0xe000_0000 0x4006_1000 0x4006_0000 dmac 0x4004_0000 0x4003_f000 ext-bus i/f 0x7000_0000 0x4003_b000 0x6000_0000 0x4003_a000 watch counter 0x4003_9000 crc 0x4003_8000 mfs 0x4400_0000 0x4003_6000 0x4200_0000 0x4003_5000 lvd ctrl 0x4003_4000 reserved 0x4000_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4003_1000 int-req.read 0x2400_0000 0x4003_0000 exti 0x4002_f000 reserved 0x2200_0000 0x4002_e000 cr trim 0x4002_8000 0x2008_0000 0x4002_7000 a/dc 0x2000_0000 sram1 0x4002_6000 qprc 0x1fff_0000 sram0 0x4002_5000 base timer 0x4002_4000 ppg 0x0010_2000 0x4002_3000 reserved 0x0010_0000 security/cr trim 0x4002_2000 mft unit2 0x4002_1000 mft unit1 0x4002_0000 mft unit0 0x4001_6000 0x4001_5000 dual timer 0x0000_0000 0x4001_3000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f reserved cortex-m3 private peripherals reserved reserved reserved reserved reserved reserved reserved external device area reserved reserved reserved 32mbyte bit band alias reserved see the next page memory map (2) for the memory size details. 32mbyte bit band alias reserved reserved on-chip flash peripherals
document number: 002 - 04683 re v.*c page 74 of 132 mb9b110t series memory map (2) see "mb9b d10t / 610t / 510t / 410t / 310t/210t/110t series flash programming manual" for sector structure of flash. mb9bf118s/t mb9bf117s/t mb9bf116s/t 0x2008_0000 0x2008_0000 0x2008_0000 0x2001_0000 0x2001_c000 0x2000_8000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_8000 0x1fff_4000 0x1fff_0000 0x0010_2000 0x0010_2000 0x0010_2000 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x000c_0000 0x0008_0000 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) flash 768kbyte flash 512kbyte sa8-9(48kbx2) sa10-23(64kbx14) sa8-9(48kbx2) sa8-9(48kbx2) sa10-19(64kbx10) sa10-15(64kbx6) reserved reserved reserved sram1 32kbyte reserved reserved sram0 32kbyte sram0 48kbyte reserved sram1 64kbyte sram0 64kbyte reserved flash 1mbyte reserved sram1 48kbyte
document number: 002 - 04683 re v.*c page 75 of 132 mb9b110t series peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit0 0x4002_1000 0x4002_1fff multi - function timer unit1 0x4002_2000 0x4002_3fff multi - function timer unit2 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter (qprc) 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff built - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt 0x4003_1000 0x4003_1fff interrupt source check register 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5fff low - voltage detector 0x4003_ 6 000 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_efff reserved 0x4003_f000 0x4003_ffff external bus interface 0x4004_0000 0x400 5 _ffff ahb reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_ 1 000 0x41ff_ffff reserved
document number: 002 - 04683 re v.*c page 76 of 132 mb9b110t series 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx =0 this is the period when the initx pin is the " l " level. ? initx=1 this is the period when the initx pin is the " h " level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 0 " . ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 1 " . ? input enabled indicates that the input function can be used. ? internal input fixed at " 0 " this is the status that the input function cannot be used. internal input is fixed at " l " . ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode.if a built - in peripheral function is operating, the output follows the peripheral function.if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used.
document number: 002 - 04683 re v.*c page 77 of 132 mb9b110t series list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enable hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop * 1 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop * 1 / internal input fixed at " 0 " c initx input pin pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled e jtag selected hi - z pull - up/ input enabled pull - up/ input enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z/ internal input fixed at " 0 " f trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output external interrupt enabled selected maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " g trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 "
document number: 002 - 04683 re v.*c page 78 of 132 mb9b110t series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 h external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " i gpio selected, resource selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " j nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " k analog input selected hi - z hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ intern al input fixed at " 0 " / analog input enabled gpio selected, or resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " l external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state analog input selected hi - z hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled gpio selected, or resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " m gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled
document number: 002 - 04683 re v.*c page 79 of 132 mb9b110t series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 n gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enable hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop * 2 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop * 2 / internal input fixed at " 0 " o gpio selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " p mode input pin input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ input enabled q gpio selected, resource selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " r external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or resource other than above selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " * 1: oscillation is stopped at sub timer mode, low - speed cr timer mode, and stop mode. * 2: oscillation is stopped at stop mode.
document number: 002 - 04683 re v.*c page 80 of 132 mb9b110t series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1, * 2 vcc vss - 0.5 vss + 6.5 v analog power supply voltage * 1, * 3 avcc vss - 0.5 vss + 6.5 v analog reference voltage * 1, * 3 avrh vss - 0.5 vss + 6.5 v input voltage * 1 v i vss - 0.5 vcc + 0.5 ( 6.5 v) v vss - 0.5 vss + 6.5 v 5 v tolerant analog pin input voltage * 1 v ia vss - 0.5 avcc + 0.5 ( 6.5 v) v output voltage * 1 v o vss - 0.5 vcc + 0.5 ( 6.5 v) v clamp maximum current i clamp - 2 +2 ma * 7 clamp total maximum current [i clamp ] +20 ma * 7 " l " level maximum output current * 4 i ol - 10 ma 4 ma type 20 ma 8 ma type 20 ma 12 ma type 39 ma p80,p81,p82,p83 " l " level average output current * 5 i olav - 4 ma 4 ma type 8 ma 8 ma type 12 ma 12 ma type 18.5 ma p80,p81,p82,p83 " l " level total maximum output current i ol - 100 ma " l " level total average output current * 6 i olav - 50 ma " h " level maximum output current * 4 i oh - - 10 ma 4 ma type - 20 ma 8 ma type - 20 ma 12 ma type - 39 ma p80,p81,p82,p83 " h " level average output current * 5 i ohav - - 4 ma 4 ma type - 8 ma 8 ma type - 12 ma 12 ma type - 20.5 ma p80,p81,p82,p83 " h " level total maximum output current i oh - - 100 ma " h " level total average output current * 6 i ohav - - 50 ma power consumption p d - 1000 mw storage temperature t stg - 55 + 150 c * 1 : these parameters are based on the condition that vss = avss = 0.0 v. * 2 : v cc must not drop below vss - 0.5 v. * 3 : ensure that the voltage does not to exceed v cc + 0. 5 v, for example, when the power is turned on. * 4 : the maximum output current is the peak value for a single pin. * 5 : the average output is the average current for a single pin over a period of 100 ms. * 6 : the total average output current is the average current for all pins over a period of 100 ms.
document number: 002 - 04683 re v.*c page 81 of 132 mb9b110t series * 7: ? see " list of pin functions " and " i /o circuit type " about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resista nce should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consumpsion modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example (i/o equivalent circuit ) . warning : ? semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, e tc.) in excess of absolute maximum ratings. do not exceed these ratings. r protection diode p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output +b input (0v to 16v)
document number: 002 - 04683 re v.*c page 82 of 132 mb9b110t series 12.2 recommended operating conditions (vss = avss = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage vcc - 2.7 * 2 5.5 v analog power supply voltage avcc - 2.7 5.5 v avcc = vcc analog reference voltage avrh - 2.7 avcc v s mooth ing capacitor c s - 1 10 f for built - in r egulator * 1 operating t emperature lqs144 , lqp176 , lbe192 t a when mounted on four - layer pcb - 40 + 85 c * 1: see " 0 c pin " in " handling devices " for the connection of the smoothing capacitor. * 2: in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or mo re, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. warning : ? the recommended operating conditions are required in order to ensure the norm al operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges.always use semiconductor devices within their recommended operating condition ranges. operation outside t hese ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 04683 re v.*c page 83 of 132 mb9b110t series 12.3 dc characteristics 12.3.1 current r ating (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks typ * 3 max * 4 run mode current icc vcc pll run mode cpu: 144 mhz, peripheral: 72 mhz, flash 2 wait, tracebuffer: on, frwtr.rwt = 10, fsyndn.sd = 000, fbfcr.be = 1 100 180 ma * 1, * 5 cpu: 72 mhz, peripheral: 72 mhz,flash 0 wait, tracebuffer: off, frwtr.rwt = 00, fsyndn.sd = 000, fbfcr.be = 0 65 135 ma * 1, * 5 high - speed cr run mode cpu/ peripheral: 4 mhz [ 2 ] , flash 0 wait, frwtr.rwt = 00, fsyndn.sd = 000 6 57.8 ma * 1 sub run mode cpu/ peripheral: 32 khz, flash 0 wait, frwtr.rwt = 00, fsyndn.sd = 000 1.3 51.7 ma * 1 , * 6 low - speed cr run mode cpu/ peripheral: 100 khz, flash 0 wait, frwtr.rwt = 00, fsyndn.sd = 000 1.3 51.7 ma * 1 sleep mode current iccs pll sleep mode peripheral: 72 mhz 30 89 ma * 1, * 5 high - speed cr sleep mode peripheral: 4 mhz * 2 4.5 55.9 ma * 1 sub sleep mode peripheral: 32 khz 1.2 51.6 ma * 1, * 6 low - speed cr sleep mode peripheral: 100 khz 1.2 51.6 ma * 1 * 1: when a l l ports are fixed. * 2: when setting it to 4 mhz by trimming. * 3 : t a = + 25c, v cc = 5.5 v * 4 : t a = + 8 5c, v cc = 5.5 v * 5: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit )
document number: 002 - 04683 re v.*c page 84 of 132 mb9b110t series (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks typ * 2 max * 2 timer mode current i cct vcc main timer mode t a = + 25 c, when lvd is off 4 10 ma * 1, * 3 t a = + 85 c, when lvd is off - 55 ma * 1, * 3 sub timer mode t a = + 25 c, when lvd is off 1.1 5 ma * 1 , * 4 t a = + 85 c, when lvd is off - 50 ma * 1 , * 4 stop mode current i cch stop mode t a = + 25 c, when lvd is off 1 5 ma * 1 t a = + 85 c, when lvd is off - 50 ma * 1 * 1: when a l l ports are fixed. * 2 : v cc = 5.5 v * 3: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 4 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) low - v oltage d etection current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 8 5c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cclvd vcc at operation for interrupt 4 7 a at not detect flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 8 5c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 12 14 ma a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 8 5c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.57 0.7 2 ma at stop 0.06 35 a reference power supply current i ccavrh avrh at 1unit operation avrh=5.5 v 1.1 1.96 ma at stop 0.06 4 a
document number: 002 - 04683 re v.*c page 85 of 132 mb9b110t series 12.3.2 pin characteristics (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0, md1 - vcc 0.8 - vcc + 0.3 v [ 1 ] 5 v tolerant input pin - vcc 0.8 - vss + 5.5 v ttl schmitt input pin - 2.0 - vcc + 0.3 v " l " level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0, md1 - vss - 0.3 - vcc 0.2 v [ 1 ] 5 v tolerant input pin - vss - 0.3 - vcc 0.2 v ttl schmitt input pin - vss - 0.3 - 0.8 v "h" level output voltage v oh 4 ma type vcc 4.5 v , i oh = - 4 ma vcc - 0.5 - vcc v [ 1 ] vcc < 4.5 v , i oh = - 2 ma 8 ma type vcc 4.5 v , i oh = - 8 ma vcc - 0.5 - vcc v [ 1 ] vcc < 4.5 v , i oh = - 4 ma 12 ma type vcc 4.5 v , i oh = - 12 ma vcc - 0.5 - vcc v vcc < 4.5 v , i oh = - 8 ma p80, p81, p82, p83 vcc 4.5 v , i oh = - 20.5 ma vcc - 0.4 - vcc v [2] vcc < 4.5 v , i oh = - 13.0 ma
document number: 002 - 04683 re v.*c page 86 of 132 mb9b110t series parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v ol 4 ma type v cc 4.5 v , i o l = 4 ma vss - 0.4 v [ 1 ] v cc < 4.5 v , i o l = 2 ma 8 ma type vcc 4.5 v , i o l = 8 ma vss - 0.4 v [ 1 ] vcc < 4.5 v , i o l = 4 ma 12 ma type v cc 4.5 v , i o l = 12 ma vss - 0.4 v v cc < 4.5 v , i o l = 8 ma p80, p81, p82, p83 vcc 4.5 v , i o l = 18.5 ma vss - 0.4 v [2] vcc < 4.5 v , i o l = 10.5 ma input leak current i il - - - 5 - + 5 a pull - up resistance value r pu pull - up pin v cc 4.5 v 25 50 100 k vcc < 4.5 v 30 80 200 input capacitance c in other than vcc, vss, avcc, avss, avrh - - 5 15 pf
document number: 002 - 04683 re v.*c page 87 of 132 mb9b110t series 12.4 ac characteristics 12.4.1 main clock input characteristics (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0, x1 vcc 4.5 v 4 48 mhz when crystal oscillator is connected vcc < 4.5 v 4 20 vcc 4.5 v 4 48 mhz when using external clock vcc < 4.5 v 4 20 input clock cycle t cylh vcc 4.5 v 20.83 250 ns when using external clock vcc < 4.5 v 50 250 input clock pulse width - p wh /t cylh , p wl /t cylh 45 55 % when using external clock input clock rise time and fall time t cf, t cr - - 5 ns when using external clock internal operating c lock [ 1 ] frequency f cm - - - 144 mhz master clock f cc - - - 144 mhz base clock (hclk/fclk) f cp0 - - - 72 mhz apb0 bus clock * 2 f cp1 - - - 72 mhz apb1 bus clock * 2 f cp 2 - - - 72 mhz apb2 bus clock * 2 internal operating clock * 1 cycle time t cycc - - 6.94 - ns base clock (hclk/fclk) t cycp0 - - 13.8 - ns apb0 bus clock * 2 t cycp1 - - 13.8 - ns apb1 bus clock * 2 t cycp2 - - 13.8 - ns apb2 bus clock * 2 * 1: for more information about each internal operating clock , see " c hapter 2 - 1 : clock " in " fm3 family peripheral manual ". * 2: for about each apb bus which ea ch peripheral is connected to , see " block diagram " in this data sheet. x0
document number: 002 - 04683 re v.*c page 88 of 132 mb9b110t series 12.4.2 sub clock input characteristics (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/ t cyll x0a, x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - p wh /t cyll , p wl /t cyll 45 - 55 % when using external clock 12.4.3 internal cr oscillation characteristics high - speed internal cr (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c 3.96 4 4.04 mhz when trimming * 1 t a = 0 c to + 70 c 3.84 4 4.16 t a = - 40 c to + 85 c 3.8 4 4.2 t a = - 40 c to + 85 c 3 4 5 when not trimming f requency stability time t crwt - - - 90 s * 2 * 1: in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming. * 2: f requency stable time is time to stable of the frequency of the high - speed cr . clock after the trim value is set. after setting the trim value, the period when the frequency stability time passes can use the high - speed cr clock as a source clo ck. low - speed internal cr (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz x0 a
document number: 002 - 04683 re v.*c page 89 of 132 mb9b110t series 12.4.4 operating conditions of main and usb pll operating conditions of main pll (in the case of using main clock for input of pll) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time * 1 (lock up time) t lock 100 - - s pll input clock frequency f plli 4 - 16 mh z pll multiple rate - 13 - 75 multiple pll macro oscillation clock frequency f pllo 200 - 300 mh z main pll clock frequency * 2 f clkpll - - 144 mhz * 1: time from when the pll starts operating until the oscillation stabilizes. * 2: for more information about main pll clock (clkpll), see "chapter 2 - 1: clock" in " fm3 family peripheral manual". operating conditions of main pll (in the case of using high - speed internal cr) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time * 1 (lock up time) t lock 100 - - s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiple rate - 50 - 71 multiple pll macro oscillation clock frequency f pllo 190 - 300 mh z main pll clock frequency * 2 f clkpll - - 144 mhz * 1: time from when the pll starts operating until the oscillation stabilizes. * 2: for more information about main pll clock (clkpll), see "c hapter 2 - 1 : clock" in " fm3 family peripheral manual". note : ? make sure to input to the main pll source clock, the high - speed cr clock (clkhc) that the frequency has been trimmed. k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection high - speed cr clock (clkhc) main clock (clkmo)
document number: 002 - 04683 re v.*c page 90 of 132 mb9b110t series 12.4.5 reset input characteristics (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns 12.4.6 power - on reset timing ( vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 50 - - ms *1 power ramp rate dv/dt vcc:0.2 v to 2.70 v 0.9 - 1000 mv/s *2 time until releasing power - on reset t prt - 0.46 - 0.76 ms *1: vcc must be held below 0.2 v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of cold start (t off >50 ms). note : ? if t off cannot be satisfied designs must assert external reset(init x) at power - up and at any brownout event per 1 2 . 4. 5 . glossary vdh: detection voltage of low voltage detection reset. s ee 12.6 low - voltage detection characteristics v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 2 . 7 v
document number: 002 - 04683 re v.*c page 91 of 132 mb9b110t series 12.4.7 external bus timing external bus clock out put c haracteristics (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max out put frequency t cycle mclkout * 1 vcc 4.5 v - 50 * 2 mhz vcc < 4.5 v - 32 * 3 mhz * 1: external bus clock (mclkout) is divided clock of hclk. for more information about setting of clock divider , see "c hapter 12 : external bus interface" in " fm3 family peripheral manual ". when external bus clock is not outp ut, this characteristic does not give any effect on external bus operation. * 2: when ahb bus clock frequency is more than 100 mhz, the divider setting for mclkout must be more than 4. * 3: when ahb bus clock frequency is more than 64 mhz, the divider settin g for mclkout must be more than 4. external bus signal input/output characteristics (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v input signal output signal mclkout v ih v il v il v ih v oh v ol v ol v oh
document number: 002 - 04683 re v.*c page 92 of 132 mb9b110t series separate bus access asynchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max m oex min pulse width t oew moex vcc 4.5 v mclk n - 3 - ns vcc < 4.5 v mcsx address output delay time t csl C av mcsx[7:0], mad[24:0] vcc 4.5 v - 9 +9 ns vcc < 4.5 v - 12 +12 moex address hold time t oeh - ax moex, mad[24:0] vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 mcsx moex delay time t cs l - oe l moex, mcsx[7:0] vcc 4.5 v mclk m - 9 mclk m+9 ns vcc < 4.5 v mclk m - 12 mclk m+12 moex mcsx time t oeh - c sh vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 mcsx mdqm delay time t cs l - r dqml mcsx, mdqm[1:0] vcc 4.5 v mclk m - 9 mclk m+9 ns vcc < 4.5 v mclk m - 12 mclk m+12 data set up moe x time t ds - oe moex, madata[15:0] vcc 4.5 v 20 - ns vcc < 4.5 v 38 - moex data hold time t dh - oe moex, madata[15:0] vcc 4.5 v 0 - ns vcc < 4.5 v m wex min pulse width t wew mwex vcc 4.5 v mclk n - 3 - ns vcc < 4.5 v mwex address output delay time t weh - ax mwex, mad[24:0] vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 mcsx mwex delay time t csl - wel mwex, mcsx[7:0] vcc 4.5 v mclk n - 9 mclk n+9 ns vcc < 4.5 v mclk n - 12 mclk n+12 mwex mcsx delay time t weh - csh vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 mcsx mdqm delay time t cs l - w dqml mcsx, mdqm[1:0] vcc 4.5 v mclk n - 9 mclk n+9 ns vcc < 4.5 v mclk n - 12 mclk n+12 mcsx data output time t csl - dv mcsx, madata[15:0] vcc 4.5 v mclk - 9 mclk+9 ns vcc < 4.5 v mclk - 12 mclk+12 mwex data hold time t weh - dx mwex, madata[15:0] vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 note : ? when the external load capacitance = 30 pf. (m = 0 to 15, n = 1 to 16)
document number: 002 - 04683 re v.*c page 93 of 132 mb9b110t series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d v
document number: 002 - 04683 re v.*c page 94 of 132 mb9b110t series separate bus access synchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max address delay time t av mclk, mad[24:0] vcc 4.5 v 1 9 ns vcc < 4.5 v 12 mcsx delay time t csl mclk, mcsx[7:0] vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t cs h vcc 4.5 v 1 9 ns vcc < 4.5 v 12 moex delay time t rel mclk, moex vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t reh vcc 4.5 v 1 9 ns vcc < 4.5 v 12 data set up mclk time t ds mclk, madata[15:0] vcc 4.5 v 19 - ns vcc < 4.5 v 37 mclk data hold time t dh mclk, madata[15:0] vcc 4.5 v 0 - ns vcc < 4.5 v mwex delay time t wel mclk, mwex vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t we h vcc 4.5 v 1 9 ns vcc < 4.5 v 12 mdqm[1:0] delay time t dqml mclk, mdqm[1:0] vcc 4.5 v 1 9 ns vcc < 4.5 v 12 t dqmh vcc 4.5 v 1 9 ns vcc < 4.5 v 12 mclk data output time t od mclk, madata[15:0] vcc 4.5 v mclk+1 mclk+18 ns vcc < 4.5 v mclk+24 mclk data hold time t od mclk, madata[15:0] vcc 4.5 v 1 18 ns vcc < 4.5 v 24 note : ? when the external load capacitance = 30 pf.
document number: 002 - 04683 re v.*c page 95 of 132 mb9b110t series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s
document number: 002 - 04683 re v.*c page 96 of 132 mb9b110t series multiplexed bus access asynchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit min max multiplexed a ddress delay time t a le - chmadv male, madata[15:0] vcc 4.5 v 0 10 ns vcc < 4.5 v 20 multiplexed a ddress hold time t c hmadh vcc 4.5 v mclk n+0 mclk n+10 ns vcc < 4.5 v mclk n+0 mclk n+20 note : ? when the external load capacitance = 30 pf. (m = 0 to 15, n = 1 to 16) mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 04683 re v.*c page 97 of 132 mb9b110t series multiplexed bus access synchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk , ale vcc 4.5 v 1 9 ns vcc < 4.5 v 1 2 ns t chah vcc 4.5 v 1 9 ns vcc < 4.5 v 12 ns mclk multiplexed address delay time t chmadv m clk, madata[15:0] vcc 4.5 v 1 t od ns vcc < 4.5 v mclk multiplexed data output time t chmad x vcc 4.5 v 1 t od ns vcc < 4.5 v note : ? when the external load capacitance = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 04683 re v.*c page 98 of 132 mb9b110t series nand flash mode (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit min max m nrex min pulse width t nrew mnrex v cc 4.5 v mclk n - 3 - ns vcc < 4.5 v data setup mnrextime t ds C nre mnrex, madata[15:0] vcc 4.5 v 20 - ns vcc < 4.5 v 38 - mnrex data hold time t dh C nre mnrex, madata[15:0] vcc 4.5 v 0 - ns vcc < 4.5 v mnale mnwex delay time t aleh - nwel mnale, mnwex vcc 4.5 v mclk m - 9 mclk m+9 ns vcc < 4.5 v mclk m - 12 mclk m+12 mnale mnwex delay time t ale l - nwel mnale, mnwex vcc 4.5 v mclk m - 9 mclk m+9 ns vcc < 4.5 v mclk m - 12 mclk m+12 mncle mnwex delay time t cleh - nwel mncle, mnwex vcc 4.5 v mclk m - 9 mclk m+9 ns vcc < 4.5 v mclk m - 12 mclk m+12 mnwex mncle delay time t nweh - clel mncle, mnwex vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 mnwex min pulse width t nwew mnwex vcc 4.5 v mclk n - 3 - ns vcc < 4.5 v mnwex data output time t nwel C dv mnwex, madata[15:0] vcc 4.5 v - 9 +9 ns vcc < 4.5 v - 12 +12 mnwex data hold time t nweh C dx mnwex, madata[15:0] vcc 4.5 v 0 mclk m+9 ns vcc < 4.5 v mclk m+12 note : ? w hen the external load capacitance = 30 pf. (m=0 to 15, n=1 to 16) nand f lash read mclk mnrex madata [ 15 : 0 ] read
document number: 002 - 04683 re v.*c page 99 of 132 mb9b110t series nand flash a ddress w rite nand flash command write mclk mnale mncle madata [ 15 : 0 ] mnwex write mclk mnale mncle madata [ 15 : 0 ] mnwex write
document number: 002 - 04683 re v.*c page 100 of 132 mb9b110t series external ready input timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max mclk mrdy input setup time t rdyi mclk, mrdy vcc 4.5 v 19 - ns vcc < 4.5 v 37 when rdy is input when rdy is release d mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycles t rdyi 2 cycles t rdyi 0.5vcc
document number: 002 - 04683 re v.*c page 101 of 132 mb9b110t series 12.4.8 base timer input timing timer input timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as ck, tin) - 2 t cycp - ns trigger input timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note : ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which base timer is connected to, see " block diagram " in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 04683 re v.*c page 102 of 132 mb9b110t series 12.4.9 csio/uart timing csio (spi = 0, scinv = 0) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sck x master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 30 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , sotx - 50 - 30 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time.about the apb bus number which multi - function serial is connected to, see " block diagram " in this data sheet. ? these characteristics only guarantee the same relocate port number.for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance = 30 pf.
document number: 002 - 04683 re v.*c page 103 of 132 mb9b110t series master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe
document number: 002 - 04683 re v.*c page 104 of 132 mb9b110t series csio (spi = 0, scinv = 1 ) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 30 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , sotx - 50 - 30 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes : ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " block diagram " in this data sheet. ? these characteristics only guarantee the same relocate port number.for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf.
document number: 002 - 04683 re v.*c page 105 of 132 mb9b110t series master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe
document number: 002 - 04683 re v.*c page 106 of 132 mb9b110t series csio (spi = 1, scinv = 0) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 30 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns sot sck delay time t sovli sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , s ot x - 50 - 30 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes : ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " block diagram " in this data sheet. ? these characteristics only guarantee the same relocate port number.for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf.
document number: 002 - 04683 re v.*c page 107 of 132 mb9b110t series master mode slave mode *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe
document number: 002 - 04683 re v.*c page 108 of 132 mb9b110t series csio (spi = 1, scinv = 1 ) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions vcc < 4.5 v vcc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 30 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns sot sck delay time t sovhi sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , s ot x - 50 - 30 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes : ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " block diagram " in this data sheet. ? these characteristics only guarantee the same relocate port number.for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load c apacitance = 30 pf.
document number: 002 - 04683 re v.*c page 109 of 132 mb9b110t series master mode slave mode uart external clock input (ext = 1 ) (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min max serial clock " l" pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock " h" pulse width t shsl t cycp + 10 - ns sck fall time tf - 5 ns sck rise time tr - 5 ns sck sot sin sck sot sin s ck t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t shsl tr t slsh tf t slove v il v il v il v ih v ih v ih v oh v ol v oh v ol v ih v il v ih v il t ivshe t shixe t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh
document number: 002 - 04683 re v.*c page 110 of 132 mb9b110t series 12.4.10 external input timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t inh, t inl adtg - 2 t cycp * 1 - ns a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * 1 - ns wave form generator intxx, nmix except timer mode, stop mode 2 t cycp + 100 * 1 - ns external interrupt nmi timer mode, stop mode 500 - ns * 1 : t cycp indicates the apb bus clock cycle time. about the apb bus number which the a/d converter, multi - function timer , external interrupt are connected to , see " block diagram " in this data sheet.
document number: 002 - 04683 re v.*c page 111 of 132 mb9b110t series 12.4.11 quadrature position/revolution counter timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2 t cycp * 1 - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - bin rise time from ain pin "h" level t aubu pc_mode2 or pc_ m ode3 ain fall time from bin pin "h" level t buad pc_mode2 or pc_mode3 bin fall time from ain pin "l" level t adbd pc_mode2 or pc_mode3 ain rise time from bin pin "l" level t bdau pc_mode2 or pc_mode3 ain rise time from bin pin "h" level t buau pc_mode2 or pc_mode3 bin fall time from ain pin "h" level t aubd pc_mode2 or pc_mode3 ain fall time from bin pin "l" level t bdad pc_mode2 or pc_mode3 bin rise time from ain pin "l" level t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc="0" zin pin "l" width t zll qcr:cgsc="0" ain/bin rise and fall time from determined zin level t zabe qcr:cgsc="1" determined zin level from ain/bin rise and fall time t abez qcr:cgsc="1" * 1 : t cycp indicates the apb bus clock cycle time. about the apb bus number which quadrature position/revolution counter is connected to , see " block diagram " in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 04683 re v.*c page 112 of 132 mb9b110t series zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 04683 re v.*c page 113 of 132 mb9b110t series 12.4.12 i 2 c timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda scl t hdsta 4.0 - 0.6 - s sclclock " l " width t low 4.7 - 1.3 - s sclclock " h " width t high 4.0 - 0.6 - s (repeated) start setup time scl sda t susta 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45 * 2 0 0.9 * 3 s data setup time sda scl t sudat 250 - 100 - ns stop condition setup time scl sda t susto 4.0 - 0.6 - s bus free time between "stop condition" and "start condition" t buf 4.7 - 1.3 - s noise filter t sp 8 mhz t cycp 40 hz 2 t cycp * 4 - 2 t cycp * 4 - ns [ 5 ] 40 mhz < t cycp 60 hz 3 t cycp * 4 - 3 t cycp * 4 - ns [ 5 ] 60 mhz < t cycp 72 hz 4 t cycp * 4 - 4 t cycp * 4 - ns [ 5 ] * 1: r and c represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. * 2: the maximum t hddat must satisfy that it does not extend at least "l" period (t low ) of device's scl signal. * 3: a fast - mode i 2 c bus device can be used on a standard - mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". cycp is the apb bus clock cycle time. about the apb bus number which i 2 c is connected to, see " block di agram " in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more.to use fast - mode, set the apb bus clock at 8 mhz or more. * 5: the number of steps of the noise filter can be changed with register settings.change the number of the no ise filter steps according to apb2 bus clock frequency. sda s cl
document number: 002 - 04683 re v.*c page 114 of 132 mb9b110t series 12.4.13 etm timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk, traced[3:0 ] vcc 4.5 v 2 9 ns vcc < 4.5 v 2 15 traceclk frequency 1/ t trace traceclk vcc 4.5 v - 50 mhz vcc < 4.5 v - 32 mhz traceclk cycle time t trace vcc 4.5 v 20 - ns vcc < 4.5 v 31.25 - ns note : ? when the external load capacitance = 30 pf. hclk traceclk traced[3:0]
document number: 002 - 04683 re v.*c page 115 of 132 mb9b110t series 12.4.14 jtag timing (vcc = 2.7v to 5.5v, vss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name conditions value unit remarks min max tms, tdi setup time t jtags tck, tms, tdi vcc 4.5 v 15 - ns vcc < 4.5 v tms, tdi hold time t jtagh tck, tms, tdi vcc 4.5 v 15 - ns vcc < 4.5 v tdo delay time t jtagd tck, tdo vcc 4.5 v - 25 ns vcc < 4.5 v - 45 note : ? when the external load capacitance = 30 pf. tck tms/tdi tdo
document number: 002 - 04683 re v.*c page 116 of 132 mb9b110t series 12.5 12 - bit a/d converter electrical characteristics for the a/d converter (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v, t a = - 40 c to + 85 c ) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 4.5 lsb avrh = 2.7 v to 5.5 v differential nonlinearity - - - 2.5 lsb zero transition voltage v zt anxx - 15 mv full - scale transition voltage v fst anxx - avrh 15 mv conversion time - - 1.0 * 1 - - s avcc 4.5 v 1.2 * 1 - - avcc < 4.5 v sampling time ts - * 2 - - ns avcc 4.5 v * 2 - - avcc < 4.5 v compare clock cycle * 3 tcck - 50 - 2000 ns state transition time to operation permission tstt - - - 1.0 s analog input capacity c ain - - - 12.9 pf analog input resistance r ain - - - 2 k avcc 4.5 v 3.8 avcc < 4.5 v interchannel disparity - - - - 4 lsb analog port input leak current - anxx - - 5 a analog input voltage - anxx av ss - avrh v reference voltage - avrh 2.7 - av cc v * 1: the conversion time is the value of sampling time (ts) + compare time (tc). the condition of the minimum conversion time is the following. avcc 4.5 v, hclk=120 mhz sampling time: 300 n s compare time: 700 n s avcc < 4.5 v, hclk=120 mhz sampling time: 500 n s compare time: 700 n s ensure that it satisfies the value of the sampling time (ts) and compare clock cycle (tcck). for setting of the sampling time and compare clock cycle, see " c hapter 1 - 1 : a/d converter " in " fm3 family peripheral manual analog macro part ". the register s setting of the a/d converter are reflected in the operation according to the apb bus clock timing. the sampling clock and compare clock is generated from the base clock (hclk). about the apb bus number which the a/d converter is connected to , see " block diagram " in this data sheet. * 2: a necessary sampling time changes by external impedance. ensure that it set the sampling time to satisfy ( equation 1 ). * 3: compare time ( tc ) is the value of ( equation 2).
document number: 002 - 04683 re v.*c page 117 of 132 mb9b110t series (equation 1) ts ( r ain + rext ) c ain 9 ts: sampling time r ain : i nput resistance of a/d = 2 k at 4.5 v av cc 5.5 v i nput resistance of a/d = 3.8 k at 2.7 v av cc < 4 .5 v c ain : i nput capacity of a/d = 12.9 pf at 2.7 v av cc 5.5 v rext: output impedance of external circuit (equation 2 ) tc = tcck 14 tc: com pare time tcck: compare clock cycle rext r ain c ain analog signal source an xx analog input pin c omparator
document number: 002 - 04683 re v.*c page 118 of 132 mb9b110t series definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition point (0b0000000000000b000000000001) and the full - scale transition point (0b1111111111100b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v zt 4094 n: a/d converter digital output value. v zt : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonlinearity differential nonlinearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff avss avrh avss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 04683 re v.*c page 119 of 132 mb9b110t series 12.6 low - v oltage detection c haracteristics 12.6.1 low - v oltage detection r eset ( t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2.25 2.45 2.65 v when voltage drops released voltage vdh - 2.30 2.50 2.70 v when voltage rises 12.6.2 interrupt of l ow - v oltage d etection ( t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0000 2.58 2.8 3.02 v when voltage drops released voltage vdh 2.67 2.9 3.13 v when voltage rises detected voltage vdl svhi = 0001 2.76 3.0 3.24 v when voltage drops released voltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 0010 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.04 3.3 3.56 v when voltage rises detected voltage vdl svhi = 0011 3.31 3.6 3.88 v when voltage drops released voltage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl svhi = 0100 3.40 3.7 3.99 v when voltage drops released voltage vdh 3.50 3.8 4.10 v when voltage rises detected voltage vdl svhi = 0111 3.68 4.0 4.32 v when voltage drops released voltage vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svhi = 1000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 1001 3.86 4.2 4. 53 v when voltage drops released voltage vdh 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 4032 t cycp * 1 s * 1 : t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 04683 re v.*c page 120 of 132 mb9b110t series 12.7 flash memory write/erase characteristics 12.7.1 write / erase time ( vcc = 2.7v to 5.5v , t a = - 40 c to + 85 c ) parameter value unit remarks typ * 1 max * 1 sector erase time large sector 0. 7 3.7 s includ es write time prior to internal erase small sector 0.3 1.1 half word (16 - bit) write time 12 384 s not including system - level overhead time. chip erase time 13.6 68 s includes write time prior to internal erase * 1 : the typical value is immediately after shipment , the maximam value is guarantee value under 100,000 cycle of erase/write . 12.7.2 w rite cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1,000 20 * 1 10,000 10 * 1 100,000 5 * 1 * 1 : at average + 85 c
document number: 002 - 04683 re v.*c page 121 of 132 mb9b110t series 12.8 return time from low - power consumption mode 12.8.1 return f actor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 85 c ) parameter symbol value unit remarks typ max * 1 sleep mode ticnt t cycc ns high - speed cr timer mode, main timer mode, pll timer mode 40 80 s low - speed cr timer mode 453 737 s sub timer mode 453 737 s stop mode 453 737 s * 1 : the maximum value depends on the accuracy of built - in cr. operation example of return from l ow - p ower consumpt ion mode (by external interrupt * 1 ) * 1 : external interrupt is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 04683 re v.*c page 122 of 132 mb9b110t series operation example of return from low - power consumption mode (by internal resource interrupt * 1 ) * 1 : internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each l ow - p ower consumption modes. see "c hapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual about the return factor from l ow - p owe r consumption mode. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state befor e the low - power consumption mode transition. see "chapter 6 : low power consumption mode" in " fm3 family peripheral manual ". i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 04683 re v.*c page 123 of 132 mb9b110t series 12.8.2 return f actor: reset the return time from low - power consumption mode is indicated a s follows. it is from releasing reset to starting the program operation. return c ount t ime ( v cc = 2.7v to 5.5v , t a = - 40 c to + 85 c ) parameter symbol value unit remarks typ max * 1 sleep mode trcnt 321 461 s high - speed cr timer mode, main timer mode, pll timer mode 321 461 s low - speed cr timer mode 441 701 s sub timer mode 441 701 s stop mode 441 701 s * 1 : the maximum value depends on the accuracy of built - in cr. operation example of return from l ow - p ower consumption mode (by initx) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 04683 re v.*c page 124 of 132 mb9b110t series operation example of return from low power consumption mode (by internal resource reset * 1 ) * 1 : internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "c hapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6 : low power consumption mode" in " fm3 family peripheral manual ". ? the time during the power - on reset/low - voltage detection reset is excluded. see " 12.4.6 power - on reset timing in 12.4 ac characteristics in electrical characteristics " for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation s tabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 04683 re v.*c page 125 of 132 mb9b110t series 13. ordering information part number on - chip flash memory on - chip sram package packing mb9bf116spmc - g k7 e1 512 kbyte 64 kbyte plastic ? lqfp 144 - pin (0.5 mm pitch) , ( lqs144 ) tray mb9bf117spmc - g k7 e1 768 kbyte 96 kbyte mb9bf118spmc - g k7 e1 1 mbyte 128 kbyte mb9bf116tpmc - g k7 e1 512 kbyte 64 kbyte plastic ? lqfp 176 - pin (0.5 mm pitch) , ( lqp176 ) mb9bf117tpmc - g k7 e1 768 kbyte 96 kbyte mb9bf118tpmc - g k7 e1 1 mbyte 128 kbyte mb9bf116tbgl - g k7 e1 512 kbyte 64 kbyte plastic ? pfbga 192 - pin (0.8 mm pitch) , ( lbe192 ) mb9bf117tbgl - g k7 e1 768 kbyte 96 kbyte mb9bf118tbgl - g k7 e1 1 mbyte 128 kbyte
document number: 002 - 04683 re v.*c page 126 of 132 mb9b110t series 14. package dimensions package type package code lqfp 176 lqp176 002 - 15150 ** d i mensi o n s s ymb o l m i n . n o m . max. a 1 . 7 0 a1 0 . 0 5 0 . 1 5 b 0 . 1 7 0 . 2 2 0 . 2 7 c 0 . 0 9 0 . 2 0 d 2 6 . 0 0 b sc d 1 2 4 . 0 0 b sc e 0 . 5 0 bs c e e1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 2 6 . 0 0 b sc 2 4 . 0 0 b sc 0 . 3 0 0 . 5 0 0 . 7 0 0 8 1 17 6 e d 1 d e e 1 3 3 0. 0 8 c a - b d b 0. 1 0 c a - b d 8 7 5 2 2 0. 0 8 c a a ' s ea t in g p l an e 4 5 7 4 5 7 a a 1 0. 2 5 1 0 l 1 l b s e c t i o n a - a ' c 9 6 0. 2 0 c a - b d s i de view top view b ottom view 1 17 6 4 4 4 5 8 8 8 9 13 2 13 3 4 4 4 5 8 8 2 3 1 9 8 13 3 package ou t line, 1 76 le a d l q f p 24.0x24.0x1.7 mm lq p 176 r ev * *
document number: 002 - 04683 re v.*c page 127 of 132 mb9b110t series package type package code lqfp 144 lqs144 002 - 13015 * a d i m e n s i o n s sym b o l m i n . n om . m ax . a 1 . 7 0 a 1 0 . 0 5 0 . 1 5 b 0 . 1 7 0 . 2 7 c 0 . 0 9 0 . 2 0 d 22.00 bsc d 1 20.00 bsc e 0.50 bsc e e 1 l 0 . 4 5 0 . 6 0 0 . 7 5 l1 0 . 3 0 0 . 5 0 0 . 7 0 22.00 bsc 20.00 bsc 0 . 2 2 1 14 4 d 1 d e e e 1 0.2 0 c a - b d 0.0 8 c a - b d b 0.1 0 c a - b d a a ' s e a t i n g plan e 0.0 8 c a a 1 0 . 2 5 10 l 1 l b se c t ion a-a ' c 9 4 5 7 3 3 8 7 5 2 2 4 5 7 6 14 4 d 1 d e e 1 4 5 7 3 4 5 7 3 6 3 7 7 2 7 3 10 8 10 9 3 7 7 2 10 9 3 6 1 8 0 1 3 7 s ide vie w t o p v i e w b o tt o m vie w package ou t line, 1 44 le a d l q f p 20 . 0x20 . 0x1 . 7 m m lq s144 r ev * a
document number: 002 - 04683 re v.*c page 128 of 132 mb9b110t series package type package code fbga 192 lbe192 002 - 13493 ** 2 . d i m e n si o n s a nd t ol e r a nc es me t h ods per asme y14.5-2009 . t h i s ou t l i n e c o n f or m s to j e p 9 5, s e c t ion 4.5 . 3 . ba ll p o si t i o n d esi g n a t i o n p e r jep95, section 3, spp-010 . 4 . "e" r ep r ese n t s t h e solder ball grid pitch . 5 . s y m b o l " m d " i s t h e b all m a t r i x s i z e i n t h e " d " d i r ec tio n . s y m b o l " m e " i s t h e b all m a t r i x s i z e i n t h e "e" d ir e c tio n . n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a t r i x s i z e m d x me . 6 . d i m e n s i o n " b " i s m e a s u r e d a t t h e m a x i m u m b a l l d ia m e t e r i n a p l a n e p a r a l l e l to d a t u m c . 7. "s d " a n d " s e" a r e m e a s u r e d w i t h r e s p e c t to d a t u m s a a n d b an d d e f i n e t h e p o s i t i o n o f t h e c e n t e r s o l d e r b a l l i n t h e o u t e r r o w . w h e n t h e r e i s a n o d d n u m b e r o f s o l d e r b a l l s i n t h e o u t e r r o w , "sd" or " se " = 0 . w h e n t h e r e i s a n e v e n n u m b e r of sol d e r b all s i n t h e o u t e r row , "sd" = ed / 2 a nd " se " = e e / 2 . 1. all d i m e n s ion s a r e i n m i lli m e t ers . 8 . a 1 c o r n e r to b e i d e n t i f i e d b y c h a m f e r , l a s e r o r i n k ma r k . m e t a lli z e d m a r k i n d e n t a t ion o r ot h er means . 9 . " + " i n d i c a t e s t h e t h eo r e t i c a l c e n t e r of d e pop u l a t e d ba ll s . n o t e s nom. m i n . e 12.00 bsc d a 1 a 12.00 bsc sym b o l m ax . 1. 4 5 d i m e n s i o n s 0. 2 5 d 1 e 1 me md n 14 14 192 b 0. 3 5 0. 5 5 0. 4 5 ee ed s d / s e 0.80 bsc 0.80 bsc 0.40 bsc 10.40 bsc 10.40 bsc 0. 3 5 0. 4 5 a 0 . 2 0 c 2 x b 0 . 2 0 c 2 x i n d e x m a r k p i n a 1 cor n e r 8 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 1 92 x b 0 . 0 8 c a b 6 7 7 d e t a i l a s i d e vie w 0 . 1 0 c c d e t a i l a b o tt o m vie w t o p v i e w m p 1 2 1 3 1 4 n 12 . 00x12 . 00 x1.45 mm l be192 r ev * * package ou t line, 1 92 b all f b g a
document number: 002 - 04683 re v.*c page 129 of 132 mb9b110t series 15. major changes spansion publication number: ds706 - 0001 6 page section change results revision 1.0 - - initial release revision 2.0 9 to 1 1 pin assignment added the description of "note". 70 , 71 handling devices ? revised the description of " ? c pin". ? added the description of " ? base timer". 72 block diagram corrected the figure. ? tioa: input input/output ? tiob: output input 82 electrical characteristics 12. 2 . recommended operating conditions ? added the "smoothing capacitor (c s )". ? added the footnote. 8 7 12. 4 . a c characteristics 12.4.1. main clock input characteristics added " i nternal operating clock frequency (f cm ) : master clock". 8 9 12.4.4.1 operating conditions of main pll (in the case of using main clock for input of pll) added "main pll clock frequency (f clkpll ) ". 12.4.4.2 operating conditions of main pll (in the case of using built - in high - speed cr clock for the input clock of the main pll) 1 16 12. 5. 12 - bit a/d converter 12.5.1 electrical c haracteristics for the a/d c onverter ? ? added the symbol. ? ? deleted the following pin name. ? "sampling time" ? "compare clock cycle" ? "state transition time to operation permission" ? "analog input capacity" ? "analog input resistance" ? corrected the value of "compare clock cycle (tcck) ". max: 10000 2000 revision 2.1 - - company name and layout design change revision 3.0 1 features external bus interface ? added the description of maximum area size 9 , 10 pin assignment ? added swclk and swdio and swo 5 8 to 64 i/o circuit type ? ? added the description of i 2 c to the type of e, f, i, ? added about +b input 6 9 handling devices added " 7.2 s tabilizing power supply voltage" 6 9 handling devices 7.3 c rystal oscillator circuit added the following description "evaluate oscillation of your using crystal oscillator by your mount board." 70 handling devices 7.6 c pin changed the description 72 block diagram modified the block diagram 73 memory map 10.1 memory map(1) modified the area of "extarnal device area" 74 memory map 10.2 memory map(2) added the summary of flash memory sector and the note
document number: 002 - 04683 re v.*c page 130 of 132 mb9b110t series page section change results 80, 81 electrical characteristics 12.1 absolute maximum ratings ? ? added the clamp maximum current ? added the output current of p80, p81, p82, p83 ? added about +b input 82 electrical characteristics 12. 2. recommended operation conditions ? ? modified the minimum value of analog reference voltage ? added smoothing capacitor ? added the note about less than the minimum power supply voltage 83, 48 electrical characteristics 12. 3. dc characteristics 12.3.1 current rating ? ? changed the table format ? added main timer mode current ? added flash memory current ? moved a/d converter current 8 8 electrical characteristics 12. 4. ac characteristics 12.4.3 built to in cr oscillation characteristics ? added frequency stability time at built to in high to speed cr 90 electrical characteristics 12. 4. ac characteristics 12.4.6 power to on reset timing ? ? added time until releasing power to on reset ? changed the figure of timing 91 electrical characteristics 12. 4. ac characteristics 12.4.7 external bus timing ? modified data output time 106 - 109 electrical characteristics 12. 4. ac characteristics 12.4.9 csio/uart timing ? ? modified from uart timing to csio/uart timing ? changed from internal shift clock operation to master mode ? changed from external shift clock operation to slave mode 1 16 electrical characteristics 12. 5. 12bit a/d converter ? ? added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full to scale transition voltage ? added conversion time at avcc < 4.5 v ? modified stage transition t ime to operation permission ? modified the minimum value of reference voltage 1 23 to 1 24 electrical characteristics 12. 8. return time from low to power consumption mode ? added return time from low to power consumption mode 1 25 ordering information ? change to full part number n ote : ? please see document history about later revised information.
document number: 002 - 04683 re v.*c page 131 of 132 mb9b110t series document history document title: mb9b110t series 32 - bit arm? cortex? - m3 fm3 microcontroller document number: 002 - 04683 revision ecn orig. of change submission date description of change ** - t oyo 02/10/2015 migrated to cypress and assig ned document number 002 - 04683 . no change to document contents or format. *a 5200957 to yo 04 / 07 /201 6 updated to cypress template *b 5560212 yska 03 / 0 9 /201 7 updated 12.4. 6 power - on reset timing. changed parameter from power supply rising time(tr)[ms] to power ramp rate(dv/dt)[mv/us] and added some comments ( page 90 ) added notes for jtag ( page 5 7 ), c hanged j - tag to jtag in 4 .2 list of pin functions ( page 3 7 ) updated package code and dimensions as follows ( page 7 - 1 0 , 82 , 12 6 - 1 2 9 ) fpt - 144p - m08 - > lqs144, fpt - 176p - m07 - > lqp176, bga - 192p - m06 - > lbe192 corrected the following statement analog port input current ? analog port input leak current in chapter 12.5. 12 - bit a/d converter ( page 117 ) added the baud rate spec in 12.4.10 csio/uart timing.( page 103 , 105 , 107 , 109 ) delet ed mpns below from 13. ordering information ( page 12 6 ) mb9bf116spmc - ge1, mb9bf116tbgl - ge1, mb9bf116tpmc - ge1, mb9bf117spmc - ge1, mb9bf117tbgl - ge1, mb9bf117tpmc - ge1, mb9bf118spmc - ge1, mb9bf118tbgl - ge1, mb9bf118tpmc - ge1 added mpns below to 13. ordering information ( page 12 6 ) mb9bf11 6spmc - gk7e1, mb9bf11 6tbgl - gk7e1, mb9bf11 6tpmc - gk7e1, mb9bf11 7spmc - gk7e1, mb9bf11 7tbgl - gk7e1, mb9bf11 7tpmc - gk7e1, mb9bf11 8spmc - gk7e1, mb9bf11 8tbgl - gk7e1, mb9bf11 8tpmc - gk7e1 *c 5797545 ysat 0 7 / 1 1 /2017 adapted new cypress logo
document number: 002 - 04683 rev.*c july 11, 2017 page 132 of 132 mb9b110t series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, v isit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb contr ollers cypress.com/ usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semiconductor corporation, 201 1 - 201 7 . this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress) . this document, including any software or firmware included or referenced in this document (software), is owned by cypress under the intell ectual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherw ise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for s oftware provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only intern ally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) under those claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import t he software solely for use with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this document or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the r ight to make changes to this document without further notice. cypress does not assume any liability arising out of the applic ation or use of any product or circuit described in this document. any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life - support devices or systems, other medic al devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances ma nagement, or other uses where the failure of the device or system could cause personal injury, death, or property damage (unintend ed uses). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products . you shall indemnify and hold cypress harmless from and against all claims, costs, damages, and othe r liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress produ cts. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and t raveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names an d brands may be claimed as property of their respective owners.

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